Design Optimizations for Tiled Partially Reconfigurable Systems

Koester M, Luk W, Hagemeyer J, Porrmann M, Rückert U (2010)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19(6): 1048-1061.

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Zeitschriftenaufsatz | Veröffentlicht | Englisch
Abstract / Bemerkung
In partially reconfigurable architectures, system components can be dynamically loaded and unloaded allowing resources to be shared over time. Dynamic system components are represented by partial reconfiguration (PR) modules. In comparison to a static system, the design of a partially reconfigurable system requires additional design steps, such as partitioning the device resources into static and dynamic regions. We present the concept of tiled PR regions, which enables a flexible online-placement of PR modules. Dynamic reconfiguration requires a suitable communication infrastructure to interconnect the static and dynamic system components. We present an embedded communication macro, a communication infrastructure that interconnects PR modules in a tiled PR region. Efficient online-placement of PR modules depends not only on the placement algorithm, but also on design-time aspects such as the chosen synthesis regions of the PR modules. We propose a design method for selecting suitable synthesis regions for the PR modules aiming to optimize their placement at run-time.
Erscheinungsjahr
Zeitschriftentitel
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Band
19
Zeitschriftennummer
6
Seite
1048-1061
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eISSN
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Koester M, Luk W, Hagemeyer J, Porrmann M, Rückert U. Design Optimizations for Tiled Partially Reconfigurable Systems. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2010;19(6):1048-1061.
Koester, M., Luk, W., Hagemeyer, J., Porrmann, M., & Rückert, U. (2010). Design Optimizations for Tiled Partially Reconfigurable Systems. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 19(6), 1048-1061. doi:10.1109/TVLSI.2010.2044902
Koester, M., Luk, W., Hagemeyer, J., Porrmann, M., and Rückert, U. (2010). Design Optimizations for Tiled Partially Reconfigurable Systems. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19, 1048-1061.
Koester, M., et al., 2010. Design Optimizations for Tiled Partially Reconfigurable Systems. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 19(6), p 1048-1061.
M. Koester, et al., “Design Optimizations for Tiled Partially Reconfigurable Systems”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, 2010, pp. 1048-1061.
Koester, M., Luk, W., Hagemeyer, J., Porrmann, M., Rückert, U.: Design Optimizations for Tiled Partially Reconfigurable Systems. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 19, 1048-1061 (2010).
Koester, M., Luk, W., Hagemeyer, Jens, Porrmann, Mario, and Rückert, Ulrich. “Design Optimizations for Tiled Partially Reconfigurable Systems”. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19.6 (2010): 1048-1061.