Mixed Mode VLSI Implementation of a Neural Associative Memory

Heittmann A, Rückert U (2002)
Analog Integrated Circuits and Signal Processing 30: 159-172.

Journal Article | Published | English

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A mixed mode digital/analog special purpose VLSI hardware implementation of an associative memory with neural architecture is presented. The memory concept is based on a n×m matrix architecture with binary storage elements holding the connection weights. To enhance the processing speed analog circuit techniques are applied to implement the algorithm for the association. Although analog circuits suffer from device mismatch a moderate precision of the circuit is acceptable since for the given associative memory model only few parts of the circuit participate on the performed information processing steps. Thus, the information processing elements can be integrated very densely on one chip and hence large scale integration with a large number of connection weights is feasible
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Heittmann A, Rückert U. Mixed Mode VLSI Implementation of a Neural Associative Memory. Analog Integrated Circuits and Signal Processing. 2002;30:159-172.
Heittmann, A., & Rückert, U. (2002). Mixed Mode VLSI Implementation of a Neural Associative Memory. Analog Integrated Circuits and Signal Processing, 30, 159-172.
Heittmann, A., and Rückert, U. (2002). Mixed Mode VLSI Implementation of a Neural Associative Memory. Analog Integrated Circuits and Signal Processing 30, 159-172.
Heittmann, A., & Rückert, U., 2002. Mixed Mode VLSI Implementation of a Neural Associative Memory. Analog Integrated Circuits and Signal Processing, 30, p 159-172.
A. Heittmann and U. Rückert, “Mixed Mode VLSI Implementation of a Neural Associative Memory”, Analog Integrated Circuits and Signal Processing, vol. 30, 2002, pp. 159-172.
Heittmann, A., Rückert, U.: Mixed Mode VLSI Implementation of a Neural Associative Memory. Analog Integrated Circuits and Signal Processing. 30, 159-172 (2002).
Heittmann, Arne, and Rückert, Ulrich. “Mixed Mode VLSI Implementation of a Neural Associative Memory”. Analog Integrated Circuits and Signal Processing 30 (2002): 159-172.
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