222 Publikationen
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2023 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2982048VEDLIoT. Next generation accelerated AIoT systems and applicationsPUB | DOI
Mika, Kevin, VEDLIoT. Next generation accelerated AIoT systems and applications. CF '23: Proceedings of the 20th ACM International Conference on Computing Frontiers (). New York, NY, 2023 -
2020 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2942756Resource-efficient bio-inspired visual processing on the hexapod walking robot HECTOR.PUB | PDF | DOI | WoS | PubMed | Europe PMC
Meyer, Hanno Gerd, Resource-efficient bio-inspired visual processing on the hexapod walking robot HECTOR.. PloS one 15 (4). , 2020 -
2019 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2933490Numerical and Experimental Evaluation of Error Estimation for Two-Way Ranging MethodsPUB | PDF | DOI | Download (ext.) | WoS | PubMed | Europe PMC
Lian Sang, Cung, Numerical and Experimental Evaluation of Error Estimation for Two-Way Ranging Methods. Sensors 19 (3). , 2019 -
2019 | Datenpublikation | PUB-ID: 2939390Supplementary Experimental Data for the Paper entitled Numerical and Experimental Evaluation of Error Estimation for Two-Way Ranging MethodsPUB | Dateien verfügbar | DOI
Lian Sang, Cung, Supplementary Experimental Data for the Paper entitled Numerical and Experimental Evaluation of Error Estimation for Two-Way Ranging Methods. (). , 2019 -
2019 | Sammelwerksbeitrag | Veröffentlicht | PUB-ID: 2920469M2DC – A Novel Heterogeneous Hyperscale Microserver PlatformPUB | DOI
Oleksiak, Ariel, M2DC – A Novel Heterogeneous Hyperscale Microserver Platform. Hardware Accelerators in Data Centers (). Cham, Switzerland, 2019 -
2018 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2982045LEGaTO. First steps towards energy-efficient toolset for heterogeneous computingPUB | DOI
Cristal, Adrian, LEGaTO. First steps towards energy-efficient toolset for heterogeneous computing. SAMOS '18. Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (). New York, NY, 2018 -
2018 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2979448LEGaTO. First steps towards energy-efficient toolset for heterogeneous computingPUB | DOI
Cristal, Adrian, LEGaTO. First steps towards energy-efficient toolset for heterogeneous computing. Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (). New York, NY, USA, 2018 -
2018 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2955564LEGaTO Project: Towards Energy-Efficient, Secure, Fault-tolerant Toolset for Heterogeneous Computing.PUB | DOI | Download (ext.)
Cristal, Adrian, LEGaTO Project: Towards Energy-Efficient, Secure, Fault-tolerant Toolset for Heterogeneous Computing.. Proceedings of the 15th ACM International Conference on Computing Frontiers (). New York, NY, 2018 -
2018 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2940681Resource-efficient Reconfigurable Computer-on-Module for Embedded Vision ApplicationsPUB | DOI
Klimeck, Daniel, Resource-efficient Reconfigurable Computer-on-Module for Embedded Vision Applications. 2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP) (). Piscataway, NJ, 2018 -
2018 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2921313An Analytical Study of Time of Flight Error Estimation in Two-Way Ranging MethodsPUB | PDF | DOI | Download (ext.)
Lian Sang, Cung, An Analytical Study of Time of Flight Error Estimation in Two-Way Ranging Methods. 2018 International Conference on Indoor Positioning and Indoor Navigation (IPIN) (). Piscataway, NJ, 2018 -
2018 | Datenpublikation | PUB-ID: 2919795Supplementary Data for the Paper entitled ''An Analytical Study of Time of Flight Error Estimation in Two-Way Ranging Methods''PUB | Dateien verfügbar | DOI
Lian Sang, Cung, Supplementary Data for the Paper entitled ''An Analytical Study of Time of Flight Error Estimation in Two-Way Ranging Methods''. (). , 2018 -
2018 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2915905CoreVA-MPSoC: A Many-core Architecture with Tightly Coupled Shared and Local Data MemoriesPUB | PDF | DOI | WoS
Ax, Johannes, CoreVA-MPSoC: A Many-core Architecture with Tightly Coupled Shared and Local Data Memories. IEEE Transactions on Parallel and Distributed Systems 29 (5). , 2018 -
2018 | Zeitschriftenaufsatz | E-Veröff. vor dem Druck | PUB-ID: 2920468FPGA-Based Vision Processing System for Automatic Online Player Tracking in Indoor SportsPUB | DOI | WoS
Ibraheem, Omar Waleed, FPGA-Based Vision Processing System for Automatic Online Player Tracking in Indoor Sports. Journal of Signal Processing Systems 91 (7). , 2018 -
2018 | Kurzbeitrag Konferenz / Poster | Veröffentlicht | PUB-ID: 2918788Accelerating Hamming Distance Comparisons for Locality Sensitive Hashing (LSH) using FPGAsPUB | PDF
Kaiser, Martin, Accelerating Hamming Distance Comparisons for Locality Sensitive Hashing (LSH) using FPGAs. 12th CeBiTec Symposium - Big Data in Medicine and Biotechnology - Abstract Book 12 (). Bielefeld, 2018 -
2018 | Report | Veröffentlicht | PUB-ID: 2918509The Comprehensive MAC Taxonomy Database: comatosePUB | PDF | DOI
Braun, Lars Dominik, The Comprehensive MAC Taxonomy Database: comatose. (). , 2018 -
2018 | Konferenzbeitrag | PUB-ID: 2921315Development of Energy Models for Design Space Exploration of Embedded Many-Core SystemsPUB
Klarhorst, Christian, Development of Energy Models for Design Space Exploration of Embedded Many-Core Systems. (). , 2018 -
2017 | Sammelwerksbeitrag | Veröffentlicht | PUB-ID: 2908972The CoreVA-MPSoC: A Multiprocessor Platform for Software-Defined RadioPUB | DOI
Sievers, Gregor, The CoreVA-MPSoC: A Multiprocessor Platform for Software-Defined Radio. Computing Platforms for Software-Defined Radio (). Cham, Switzerland, 2017 -
2017 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2937407The M2DC Approach towards Resource-efficient ComputingPUB | DOI
Agosta, Giovanni, The M2DC Approach towards Resource-efficient Computing. OPPORTUNITIES AND CHALLENGES for European Projects. Volume 1: EPS Portugal 2017/2018 (). Setúbal, Portugal, 2017 -
2017 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2912818M2DC – Modular Microserver DataCentre with heterogeneous hardwarePUB | DOI | WoS
Oleksiak, Ariel, M2DC – Modular Microserver DataCentre with heterogeneous hardware. Microprocessors and Microsystems 52 (). , 2017 -
2017 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2912815Reconfigurable Vision Processing System for Player Tracking in Indoor SportsPUB | DOI
Ibraheem, Omar Waleed, Reconfigurable Vision Processing System for Player Tracking in Indoor Sports. Conference on Design and Architectures for Signal and Image Processing (DASIP 2017) (). Piscataway, NJ, 2017 -
2017 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2909430FPGA-based Multi-Robot TrackingPUB | DOI | Download (ext.) | WoS
Irwansyah, Arif, FPGA-based Multi-Robot Tracking. Journal of Parallel and Distributed Computing 107 (). , 2017 -
2017 | Kurzbeitrag Konferenz / Poster | Veröffentlicht | PUB-ID: 2918683A Reconfigurable Heterogeneous Microserver Architecture for Energy-efficient ComputingPUB | PDF | Download (ext.)
Kaiser, Martin, A Reconfigurable Heterogeneous Microserver Architecture for Energy-efficient Computing. Third International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC'17) (). Denver, CO, 2017 -
2017 | Konferenzbeitrag | Angenommen | PUB-ID: 2912816Comparing synchronous, mesochronous and asynchronous NoCs for GALS based MPSoCPUB
Ax, Johannes, Comparing synchronous, mesochronous and asynchronous NoCs for GALS based MPSoC. IEEE 11th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-17) (). , 2017 -
2017 | Konferenzbeitrag | PUB-ID: 2909584M2DC: Modular Microserver Datacentre with Heterogeneous HardwarePUB
Oleksiak, Ariel, M2DC: Modular Microserver Datacentre with Heterogeneous Hardware. (). , 2017 -
2017 | Report | PUB-ID: 2913643Survey of FPGA applications in the period 2000 – 2015 (Technical Report)PUB | PDF | DOI
Romoth, Johannes, Survey of FPGA applications in the period 2000 – 2015 (Technical Report). (). , 2017 -
2017 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2909044From CPU to FPGA – Acceleration of Self-Organizing Maps for Data MiningPUB
Lachmair, Jan, From CPU to FPGA – Acceleration of Self-Organizing Maps for Data Mining. International Joint Conference on Neural Networks (IJCNN 2017) (). , 2017 -
2016 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2900363Performance Estimation of Streaming Applications for Hierarchical MPSoCsPUB | PDF | DOI
Flasskamp, Martin, Performance Estimation of Streaming Applications for Hierarchical MPSoCs. Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO) (). New York, NY, 2016 -
2016 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2908973OLT(RE)²: an On-Line on-demand Testing approach for permanent Radiation Effects in REconfigurable systemsPUB | DOI | WoS
Cozzi, Dario, OLT(RE)²: an On-Line on-demand Testing approach for permanent Radiation Effects in REconfigurable systems. IEEE Transactions on Emerging Topics in Computing PP (99). , 2016 -
2016 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2908974Data centres for IoT applications: The M2DC approach (Invited paper)PUB | DOI
Oleksiak, Ariel, Data centres for IoT applications: The M2DC approach (Invited paper). 2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS) (). , 2016 -
2016 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2908980The M2DC Project: Modular Microserver DataCentrePUB | DOI
Cecowski, Mariano, The M2DC Project: Modular Microserver DataCentre. 2016 Euromicro Conference on Digital System Design (DSD) (). , 2016 -
2016 | Kurzbeitrag Konferenz / Poster | PUB-ID: 2909602FiPS and M2DC: Novel Architectures for Reconfigurable Hyperscale ServersPUB | Download (ext.)
Griessl, René, FiPS and M2DC: Novel Architectures for Reconfigurable Hyperscale Servers. (). , 2016 -
2015 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2783142System-Level Analysis of Network Interfaces for Hierarchical MPSoCsPUB | PDF | DOI
Ax, Johannes, System-Level Analysis of Network Interfaces for Hierarchical MPSoCs. Proceedings of the 8th International Workshop on Network on Chip Architectures (NoCArc) (). New York, NY, USA, 2015 -
2015 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2732427Evaluation of Interconnect Fabrics for an Embedded MPSoC in 28 nm FD-SOIPUB | DOI | Download (ext.)
Sievers, Gregor, Evaluation of Interconnect Fabrics for an Embedded MPSoC in 28 nm FD-SOI. 2015 IEEE International Symposium on Circuits & Systems (ISCAS) (). , 2015 -
2015 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2760622Comparison of Shared and Private L1 Data Memories for an Embedded MPSoC in 28nm FD-SOIPUB | DOI
Sievers, Gregor, Comparison of Shared and Private L1 Data Memories for an Embedded MPSoC in 28nm FD-SOI. International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC) (). , 2015 -
2015 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2901107A resource-efficient multi-camera GigE vision IP core for embedded vision processing platformsPUB | DOI
Ibraheem, Omar Waleed, A resource-efficient multi-camera GigE vision IP core for embedded vision processing platforms. 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig) (). Piscataway, NJ, 2015 -
2015 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2901108FPGA-based circular hough transform with graph clustering for vision-based multi-robot trackingPUB | DOI
Irwansyah, Arif, FPGA-based circular hough transform with graph clustering for vision-based multi-robot tracking. 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig) (). Piscataway, NJ, 2015 -
2015 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2732419Automatische Protokollanpassung von Echtzeit-Ethernet-Standards durch FPGA-TechnologienPUB
Buda, Aurel, Automatische Protokollanpassung von Echtzeit-Ethernet-Standards durch FPGA-Technologien. (). , 2015 -
2015 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2732431Datenflussmodellierung als Methode zur Optimierung von Entwicklungsprozessen am Beispiel der LeiterplattenentwicklungPUB
Herbrechtsmeier, Stefan, Datenflussmodellierung als Methode zur Optimierung von Entwicklungsprozessen am Beispiel der Leiterplattenentwicklung. Entwurf mechatronischer Systeme 343 (). Paderborn, 2015 -
2015 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2902039FPGA-accelerated Heterogeneous Hyperscale Server Architecture for Next-Generation Compute ClustersPUB | PDF
Griessl, René, FPGA-accelerated Heterogeneous Hyperscale Server Architecture for Next-Generation Compute Clusters. (). , 2015 -
2015 | Konferenzbeitrag | PUB-ID: 2902041A 65 nm Standard Cell Library for Ultra Low-power ApplicationsPUB | DOI
Vohrmann, Marten, A 65 nm Standard Cell Library for Ultra Low-power Applications. (). , 2015 -
2014 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2698992FPGA-based Generic Architecture for Rapid Prototyping of Video Hardware Accelerators using NoC AXI4-Stream Interconnect and GigE Vision Camera InterfacesPUB
Irwansyah, Arif, FPGA-based Generic Architecture for Rapid Prototyping of Video Hardware Accelerators using NoC AXI4-Stream Interconnect and GigE Vision Camera Interfaces. (). , 2014 -
2014 | Sammelwerksbeitrag | Veröffentlicht | PUB-ID: 2732400Development of Self-Optimizing SystemsPUB | DOI
Gausemeier, Jürgen, Development of Self-Optimizing Systems. Design Methodology for Intelligent Technical Systems. Develop Intelligent Technical Systems of the Future (). Berlin Heidelberg, 2014 -
2014 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2681323Reconfigurable High Performance Architectures: How much are they ready for safety-critical applicationsPUB | DOI | Download (ext.)
Sabena, Davide, Reconfigurable High Performance Architectures: How much are they ready for safety-critical applications. Proceedings of 19th IEEE European Test Symposium (ETS) (). , 2014 -
2014 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2698994Dynamische Rekonfiguration von Echtzeit-Ethernet-Standards mit harten EchtzeitanforderungenPUB | Download (ext.)
Walter, Martin, Dynamische Rekonfiguration von Echtzeit-Ethernet-Standards mit harten Echtzeitanforderungen. (). , 2014 -
2014 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2698999Exploiting Dynamic Partial Reconfiguration for On-Line On-Demand Testing of Permanent Faults in Reconfigurable SystemsPUB | DOI | Download (ext.)
Sorrenti, Domenico, Exploiting Dynamic Partial Reconfiguration for On-Line On-Demand Testing of Permanent Faults in Reconfigurable Systems. (). , 2014 -
2014 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2699005AXI-based SpaceFibre IP CORE ImplementationPUB | DOI | Download (ext.)
Cozzi, Dario, AXI-based SpaceFibre IP CORE Implementation. (). , 2014 -
2014 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2698929CoreVA: A Configurable Resource-efficient VLIW Processor ArchitecturePUB | DOI
Hübener, Boris, CoreVA: A Configurable Resource-efficient VLIW Processor Architecture. Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing (). , 2014 -
2014 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2698930A Scalable Server Architecture for Next-Generation Heterogeneous Compute ClustersPUB | DOI | Download (ext.)
Griessl, René, A Scalable Server Architecture for Next-Generation Heterogeneous Compute Clusters. Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, EUC 2014 (). , 2014 -
2014 | Konferenzbeitrag | PUB-ID: 2681362An Inter-Processor Communication Interface for Data-Flow Centric Heterogeneous Embedded Multiprocessor SystemsPUB | DOI | Download (ext.)
Cassano, Luca, An Inter-Processor Communication Interface for Data-Flow Centric Heterogeneous Embedded Multiprocessor Systems. (). , 2014 -
2014 | Sammelwerksbeitrag | Veröffentlicht | PUB-ID: 2732260Methods of Improving the Dependability of Self-optimizing SystemsPUB | DOI
Seifried, Albert, Methods of Improving the Dependability of Self-optimizing Systems. Dependability of Self-Optimizing Mechatronic Systems (). Berlin Heidelberg, 2014 -
2014 | Sammelwerksbeitrag | Veröffentlicht | PUB-ID: 2920470The Paradigm of Self-optimizationPUB | DOI
Dellnitz, Micael, The Paradigm of Self-optimization. Design Methodology for Intelligent Technical Systems – Develop Intelligent Technical Systems of the Future (). Berlin Heidelberg, 2014 -
2013 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2560236A 65 nm 32 b Subthreshold Processor With 9T Multi-Vt SRAM and Adaptive Supply Voltage ControlPUB | DOI | WoS
Lütkemeier, Sven, A 65 nm 32 b Subthreshold Processor With 9T Multi-Vt SRAM and Adaptive Supply Voltage Control. IEEE Journal Of Solid-State Circuits 48 (1). , 2013 -
2013 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2576115Dynamisch rekonfigurierbare Hardware als Basistechnologie für intelligente technische SystemePUB | PDF
Korf, Sebastian, Dynamisch rekonfigurierbare Hardware als Basistechnologie für intelligente technische Systeme. Proceedings Wissenschaftsforum 2013 Intelligente Technische Systeme 310 (). Paderborn, 2013 -
2013 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2637667Design-Space Exploration of the Configurable 32 bit VLIW Processor CoreVA for Signal Processing ApplicationsPUB | DOI
Sievers, Gregor, Design-Space Exploration of the Configurable 32 bit VLIW Processor CoreVA for Signal Processing Applications. 2013 NORCHIP (). , 2013 -
2013 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2634649Pareto-optimal Signal Processing on Low-Power MicroprocessorsPUB | DOI | Download (ext.)
Christ, Peter, Pareto-optimal Signal Processing on Low-Power Microprocessors. Proceedings of the 12th IEEE International Conference on SENSORS (). , 2013 -
2013 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2622226A Novel Fault Tolerant and Runtime Reconfigurable Platform for Satellite Payload ProcessingPUB | DOI | WoS
Sterpone, Luca, A Novel Fault Tolerant and Runtime Reconfigurable Platform for Satellite Payload Processing. IEEE Transactions on Computers 62 (8). , 2013 -
2013 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2681289Hardening Dynamically Reconfigurable Processing Modules Architectures: A Neutron Test ExperiencePUB
Desogus, Marco, Hardening Dynamically Reconfigurable Processing Modules Architectures: A Neutron Test Experience. RADECS proceedings 2 (). , 2013 -
2013 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2681304Dynamic neutron testing of Dynamically Reconfigurable Processing Modules architecturePUB | DOI | Download (ext.)
Sterpone, Luca, Dynamic neutron testing of Dynamically Reconfigurable Processing Modules architecture. Adaptive Hardware and Systems (AHS), 2013 NASA/ESA Conference on (). , 2013 -
2013 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2634614A Systematic Approach for Optimized Bypass Configurations for Application-specific Embedded ProcessorsPUB | DOI | Download (ext.) | WoS
Jungeblut, Thorsten, A Systematic Approach for Optimized Bypass Configurations for Application-specific Embedded Processors. ACM Trans. Embed. Comput. Syst. 13 (2). , 2013 -
2013 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2576042On-Line Testing of Permanent Radiation Effects in Reconfigurable SystemsPUB | DOI
Cassano, Luca, On-Line Testing of Permanent Radiation Effects in Reconfigurable Systems. Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013 (). Piscataway, NJ, 2013 -
2013 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2575531A reconfigurable neuroprocessor for self-organizing feature mapsPUB | DOI | Download (ext.) | WoS
Lachmair, Jan, A reconfigurable neuroprocessor for self-organizing feature maps. Neurocomputing 112 (SI). , 2013 -
2012 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2559365Optimizing inter-FPGA communication by automatic channel adaptationPUB | DOI
Romoth, Johannes, Optimizing inter-FPGA communication by automatic channel adaptation. 2012 International Conference on Reconfigurable Computing and FPGAs. 5 - 7 Dec. 2012, Cancun, Mexico (). Piscataway, NJ, 2012 -
2012 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2493811gNBXe - a Reconfigurable Neuroprocessor for Various Types of Self-Organizing MapsPUB | Download (ext.)
Lachmair, Jan, gNBXe - a Reconfigurable Neuroprocessor for Various Types of Self-Organizing Maps. European Symposium on Artificial Neural Networks, Computational Intelligence and Machine Learning (). , 2012 -
2012 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2475063A 200mV 32b Subthreshold Processor with Adaptive Supply Voltage ControlPUB | DOI
Lütkemeier, Sven, A 200mV 32b Subthreshold Processor with Adaptive Supply Voltage Control. Proc. of the International Solid-State Circuits Conference (ISSCC) (). Piscataway, NJ, 2012 -
2012 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2517354A Scalable Platform for Run-time Reconfigurable Satellite Payload ProcessingPUB | DOI | Download (ext.)
Hagemeyer, Jens, A Scalable Platform for Run-time Reconfigurable Satellite Payload Processing. 2012 NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2012) (). Piscataway, NJ, 2012 -
2012 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2493814Mini-Robot's Performance Optimization via Online Reconfiguration and HW/SW Task Scheduling.PUB | DOI | Download (ext.)
Durelli, G., Mini-Robot's Performance Optimization via Online Reconfiguration and HW/SW Task Scheduling.. 19th Reconfigurable Architectures Workshop (RAW 2012) (). , 2012 -
2012 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2493813A TCMS-based architecture for GALS NoCs.PUB | DOI
Jungeblut, Thorsten, A TCMS-based architecture for GALS NoCs.. 2012 IEEE International Symposium on Circuits and Systems (). Piscataway, NJ, 2012 -
2011 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2286173Automatic HDL-Based Generation of Homogeneous Hard Macros for FPGAsPUB | DOI | Download (ext.)
Korf, Sebastian, Automatic HDL-Based Generation of Homogeneous Hard Macros for FPGAs. IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2011 : 1 - 3 May 2011, Salt Lake City, Utah, USA ; proceedings (). Piscataway, NJ, 2011 -
2011 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2493823Evaluation of Applied Intra-Disk Redundancy Schemes to Improve Single Disk Reliability.PUB | DOI | Download (ext.)
Grawinkel, M., Evaluation of Applied Intra-Disk Redundancy Schemes to Improve Single Disk Reliability.. MASCOTS2011 The 19th Annual Meeting of the IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems. (). Piscataway, NJ, 2011 -
2011 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2493819Analysis of SEU Effects in Partially Reconfigurable SoPCs.PUB | DOI
Sterpone, L., Analysis of SEU Effects in Partially Reconfigurable SoPCs.. Proceedings of NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2011) (). Piscataway, NJ, 2011 -
2011 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494507Fast Design-space Exploration with FPGA ClusterPUB | Download (ext.)
Romoth, Johannes, Fast Design-space Exploration with FPGA Cluster. DATE 2011 Workshop on Design Methods and Tools for FPGA-Based Acceleration of Scientific Computing (). , 2011 -
2011 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2476993Resource Efficiency of Scalable Processor Architectures for SDR-based Applications (Invited)PUB | Dateien verfügbar
Jungeblut, Thorsten, Resource Efficiency of Scalable Processor Architectures for SDR-based Applications (Invited). Proc. of the Radar, Communication and Measurement Conference (RADCOM) (). , 2011 -
2011 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2493623Applying dynamic reconfiguration in the mobile robotics domain: a case study on computer vision algorithms.PUB | DOI | WoS
Nava, F., Applying dynamic reconfiguration in the mobile robotics domain: a case study on computer vision algorithms.. ACM Transactions on Reconfigurable Technology and Systems (TRETS) 4 (3). , 2011 -
2011 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494510A Low-Power Vision Processing Platform for Mobile RobotsPUB | Download (ext.)
Griessl, René, A Low-Power Vision Processing Platform for Mobile Robots. Proceedings of the FPL2011 Workshop on Computer Vision on Low-Power Reconfigurable Architectures (). , 2011 -
2011 | Kurzbeitrag Konferenz / Poster | Veröffentlicht | PUB-ID: 2494497Design Flow for a Fault-Tolerant Reconfigurable Multi-FPGA Architecture for Space ApplicationsPUB
Köster, Markus, Design Flow for a Fault-Tolerant Reconfigurable Multi-FPGA Architecture for Space Applications. DATE 2011 Workshop on Design Methods and Tools for FPGA-Based Acceleration of Scientific Computing (). , 2011 -
2011 | Sammelwerksbeitrag | Veröffentlicht | PUB-ID: 2018536Design-space Exploration for Flexible WLAN HardwarePUB
Jungeblut, Thorsten, Design-space Exploration for Flexible WLAN Hardware. Cross Layer Designs in WLAN Systems (). Leicester, UK, 2011 -
2010 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2494479vMAGIC – Automatic Code Generation for VHDLPUB | DOI
Pohl, Christopher, vMAGIC – Automatic Code Generation for VHDL. newsletter edacentrum 2009 (). , 2010 -
2010 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2493826Implementation of a Dynamically Reconfigurable Processing Module for SpaceWire Networks.PUB | Download (ext.)
Dittmann, Florian, Implementation of a Dynamically Reconfigurable Processing Module for SpaceWire Networks.. Proceedings of the International SpaceWire Conference 2010 (). , 2010 -
2010 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472693RAPTOR – A Scalable Platform for Rapid Prototyping and FPGA-based Cluster ComputingPUB | PDF
Porrmann, Mario, RAPTOR – A Scalable Platform for Rapid Prototyping and FPGA-based Cluster Computing. Parallel Computing: From Multicores and GPU's to Petascale, Advances in Parallel Computing 19 (). , 2010 -
2010 | Patent | Veröffentlicht | PUB-ID: 2494087Mehrprozessor-ComputersystemPUB
Christmann, W., Mehrprozessor-Computersystem. (). , 2010 -
2010 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2286622Extending GigaNoC towards a Dependable Network-on-ChipPUB
Puttmann, Christoph, Extending GigaNoC towards a Dependable Network-on-Chip. Digest of the DAC Workshop on Diagnostic Services in Network-on-Chips (DSNOC) (). , 2010 -
2010 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2018549Design Space Exploration for Memory Subsystems of VLIW ArchitecturesPUB | DOI
Jungeblut, Thorsten, Design Space Exploration for Memory Subsystems of VLIW Architectures. 5th IEEE International Conference on Networking, Architecture, and Storage (). , 2010 -
2010 | Konferenzbeitrag | PUB-ID: 2286616A Framework for the Design Space Exploration of Software-Defined Radio ApplicationsPUB | Download (ext.)
Jungeblut, Thorsten, A Framework for the Design Space Exploration of Software-Defined Radio Applications. (). , 2010 -
2010 | Konferenzbeitrag | PUB-ID: 2286628A modular design flow for very large design space explorationsPUB | Dateien verfügbar
Jungeblut, Thorsten, A modular design flow for very large design space explorations. (). , 2010 -
2010 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2018541Resource Efficiency of Hardware Extensions of a 4-issue VLIW Processor for Elliptic Curve CryptographyPUB | PDF | DOI | Download (ext.)
Jungeblut, Thorsten, Resource Efficiency of Hardware Extensions of a 4-issue VLIW Processor for Elliptic Curve Cryptography. Advances in Radio Science 8 (). , 2010 -
2010 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2145423Design Optimizations for Tiled Partially Reconfigurable SystemsPUB | DOI | WoS
Koester, M., Design Optimizations for Tiled Partially Reconfigurable Systems. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19 (6). , 2010 -
2010 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2018557Runtime Reconfiguration of Multiprocessors Based on Compile-Time AnalysisPUB | DOI | WoS
Purnaprajna, Madhura, Runtime Reconfiguration of Multiprocessors Based on Compile-Time Analysis. ACM Transactions on Reconfigurable Technology 3 (3). , 2010 -
2010 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2018564High Level Specification of Embedded Listeners for Monitoring of Network-on-ChipsPUB | DOI
Puttmann, Christoph, High Level Specification of Embedded Listeners for Monitoring of Network-on-Chips. Proceedings of the IEEE International Symposium on Circuits and Systems (). , 2010 -
2009 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2493628vMAGIC - Automatic Code Generation for VHDLPUB | DOI | Download (ext.)
Pohl, Christopher, vMAGIC - Automatic Code Generation for VHDL. International Journal of Reconfigurable Computing, Hindawi Publishing Corporation, 2009 (Article ID 205149). , 2009 -
2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2493880Self-optimization of MPSoCs Targeting Resource Efficiency and Fault TolerancePUB | DOI
Porrmann, Mario, Self-optimization of MPSoCs Targeting Resource Efficiency and Fault Tolerance. NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2009) (). Piscataway, NJ, 2009 -
2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472673Design Optimizations to Improve Placeability of Partial Reconfiguration ModulesPUB | DOI | Download (ext.)
Koester, Markus, Design Optimizations to Improve Placeability of Partial Reconfiguration Modules. Proceedings of the International Conference on Design, Automation and Test in Europe (DATE 2009) (). Piscataway, NJ, 2009 -
2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472678Rapid Prototyping of Next-Generation Multiprocessor SoCsPUB
Porrmann, Mario, Rapid Prototyping of Next-Generation Multiprocessor SoCs. Proceedings of Semiconductor Conference Dresden, SCD 2009 (). Dresden, Germany, 2009 -
2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472686SiLLis: A Simplified Language for Monitoring and Debugging of Reconfigurable SystemsPUB
Grassi, Paolo Roberto, SiLLis: A Simplified Language for Monitoring and Debugging of Reconfigurable Systems. Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA '09) (). Las Vegas, USA, 2009 -
2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2493870A High Level Methodology for Monitoring Network-on-ChipsPUB
Grassi, Paolo Roberto, A High Level Methodology for Monitoring Network-on-Chips. Diagnostic Services in Network-on-Chips (DSNOC 2009), Workshop at Design, Automation and Test in Europe. (). , 2009 -
2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2144752Using Run-time Reconfiguration for Energy Savings in Parallel Data ProcessingPUB | PDF
Purnaprajna, Madhura, Using Run-time Reconfiguration for Energy Savings in Parallel Data Processing. Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'09, July 13-16, 2009, Las Vegas, Nevada, USA (). , 2009 -
2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2144757A Synchronization Method for Register Traces of Pipelined ProcessorsPUB | Download (ext.)
Dreesen, Ralf, A Synchronization Method for Register Traces of Pipelined Processors. Proceedings of the International Embedded Systems Symposium 2009 (IESS '09) (). Schloss Langenargen, Germany, 2009 -
2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2144891FPGA-in-the-Loop-Simulations for Dynamically Reconfigurable ApplicationsPUB | DOI
Paiz, Carlos, FPGA-in-the-Loop-Simulations for Dynamically Reconfigurable Applications. Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT'09) (). The University of New South Wales, Sydney, Australia, 9-11, Sydney, Australia, 2009 -
2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2493834Cipset for a Coherent Polarization-Multiplexed QPSK ReceiverPUB | DOI
Herath, Vijitha, Cipset for a Coherent Polarization-Multiplexed QPSK Receiver. Proceedings of OFC/NFOEC 2009 (). Piscataway, NJ, 2009 -
2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2144772InCyte ChipEstimator in Research and EducationPUB
Liß, Christian, InCyte ChipEstimator in Research and Education. CDNLive EMEA 2009 (). , 2009 -
2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2144830Design Space Exploration for Next Generation Wireless Technologies (invited talk).PUB
Jungeblut, Thorsten, Design Space Exploration for Next Generation Wireless Technologies (invited talk).. Proc. of the Electrical and Electronic Engineering for Communication Conference (EEEfCOM) 2009 (). , 2009 -
2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2144880Using a Reconfigurable Compute Cluster for the Acceleration of Neural NetworksPUB | DOI
Pohl, Christopher, Using a Reconfigurable Compute Cluster for the Acceleration of Neural Networks. Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT '09) (). Sydney, Australia, 2009 -
2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2493855Towards Real-Time Implementation of Coherent Optical CommunicationPUB | DOI
Pfau, Timo, Towards Real-Time Implementation of Coherent Optical Communication. Proceedings of OFC/NFOEC 2009 (). Piscataway, NJ, 2009 -
2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494485Manageable Dynamic Reconfiguration with EVE – Extendable VHDL EditorPUB | Download (ext.)
Pohl, Christopher, Manageable Dynamic Reconfiguration with EVE – Extendable VHDL Editor. Design Automation and Test in Europe (DATE), University Booth (). , 2009 -
2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2144724Reconfiguration ViewerPUB | PDF
Grassi, Paolo Roberto, Reconfiguration Viewer. Design Automation and Test in Europe, DATE University Booth (). Nice, France, 2009 -
2009 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2144870Run-time reconfigurability in embedded multiprocessorsPUB | DOI | Download (ext.)
Purnaprajna, Madhura, Run-time reconfigurability in embedded multiprocessors. ACM SIGARCH Computer Architecture News 37 (2). , 2009 -
2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2144782Early Exploration of Network Processor Architectures Using Cadence InCyte Chip EstimatorPUB
Liß, Christian, Early Exploration of Network Processor Architectures Using Cadence InCyte Chip Estimator. CDNLive EMEA 2009 (). , 2009 -
2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2144843FPGA-Based Realization of Self-Optimizing Drive-ControllersPUB | PDF | DOI | Download (ext.)
Paiz, Carlos, FPGA-Based Realization of Self-Optimizing Drive-Controllers. the 35th Annual Conference of the IEEE Industrial Electronics Society (IECON 2009) (). Piscataway, NJ, 2009 -
2008 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2942215Power Aware Reconfigurable Multiprocessor for Elliptic Curve CryptographyPUB | DOI
Purnaprajna, Madhura, Power Aware Reconfigurable Multiprocessor for Elliptic Curve Cryptography. 2008 Design, Automation and Test in Europe (). Piscataway, NJ, 2008 -
2008 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2493929Power Aware Reconfigurable Multiprocessor for Elliptic Curve CryptographyPUB | DOI | Download (ext.)
Purnaprajna, Madhura, Power Aware Reconfigurable Multiprocessor for Elliptic Curve Cryptography. Proceedings of DATE '08: Design, Automation and Test in Europe (). , 2008 -
2008 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494491A Hardware-in-the-Loop Design Environment for FPGAsPUB
Pohl, Christopher, A Hardware-in-the-Loop Design Environment for FPGAs. Design, Automation and Test in Europe (DATE), University Booth (). , 2008 -
2008 | Sammelwerksbeitrag | Veröffentlicht | PUB-ID: 2493607Hardware-in-the-Loop Simulations for FPGA-Based Digital Control Design.PUB | DOI
Paiz, Carlos, Hardware-in-the-Loop Simulations for FPGA-Based Digital Control Design.. Informatics in Control, Automation and Robotics 3 (). Berlin, Heidelberg, 2008 -
2008 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2493900Ultra-Fast Adaptive Digital Polarization Control in a Realtime Coherent Polarization-Multiplexed QPSK ReceiverPUB | Download (ext.)
Pfau, Timo, Ultra-Fast Adaptive Digital Polarization Control in a Realtime Coherent Polarization-Multiplexed QPSK Receiver. Proceedings of OFC/NFOEC 2008 (). , 2008 -
2008 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2493648Fast Adaptive Polarization and PDL Tracking in a Real-Time FPGA-Based Coherent PolDM-QPSK ReceiverPUB | DOI | WoS
El-Darawy, Mohamed, Fast Adaptive Polarization and PDL Tracking in a Real-Time FPGA-Based Coherent PolDM-QPSK Receiver. IEEE Photonics Technology Letters 20 (21). , 2008 -
2008 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2493667Frequency and Phase Estimation for Coherent QPSK Transmission With Unlocked DFB LasersPUB | DOI | WoS
Hoffmann, Sebastian, Frequency and Phase Estimation for Coherent QPSK Transmission With Unlocked DFB Lasers. IEEE Photonics Technology Letters 20 (18). , 2008 -
2008 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2493890FPGA-in-the-Loop Simulations with CAMEL-ViewPUB
Münch, Eckehard, FPGA-in-the-Loop Simulations with CAMEL-View. Self-optimizing Mechatronic Systems: Design the Future, 7th International Heinz Nixdorf Symposium. (). , 2008 -
2008 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2493939Resource Efficiency of Instruction Set Extensions for Elliptic Curve CryptographyPUB | DOI
Puttmann, Christoph, Resource Efficiency of Instruction Set Extensions for Elliptic Curve Cryptography. Proceedings of the 5th Internation Conference on Information Technology: New Generations, ITNG 2008 (). Piscataway, NJ, 2008 -
2008 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2493960vMAGIC – VHDL Manipulation and Automation for Reliable System DevelopmentPUB
Pohl, Christopher, vMAGIC – VHDL Manipulation and Automation for Reliable System Development. Proceedings of the 3rd International Workshop on Reconfigurable Computing Education (on CD) (). , 2008 -
2008 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494141Realtime 40 krad/s Polarization Tracking with 6 dB PDL in Digital Synchronous Polarization-Multiplexed QPSK ReceiverPUB | DOI
El-Darawy, Mohamed, Realtime 40 krad/s Polarization Tracking with 6 dB PDL in Digital Synchronous Polarization-Multiplexed QPSK Receiver. Proceedings of European Conference on Optical Communication (ECOC) (). , 2008 -
2008 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472725Hardware Virtualization Exploiting Dynamically Reconfigurable ArchitecturesPUB
Hagemeyer, Jens, Hardware Virtualization Exploiting Dynamically Reconfigurable Architectures. 1. GI/ITG KuVS Fachgespräch Virtualisierung (). , 2008 -
2008 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2493945SelfS – A Real-Time Protocol for Virtual Ring TopologiesPUB | DOI
Griese, Björn, SelfS – A Real-Time Protocol for Virtual Ring Topologies. Proceedings of the 16th International Workshop on Parallel and Distributed Real-Time Systems (WPDRTS '08), on CD (). Piscataway, NJ, 2008 -
2008 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2493957Run-time Reconfigurable MultiprocessorsPUB
Purnaprajna, M., Run-time Reconfigurable Multiprocessors. Proceedings of the 22nd International Parallel and Distributed Processing Symposium (IPDPS 2008), PhD Forum (). , 2008 -
2008 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494157Run-time Reconfigurable Cluster of ProcessorsPUB | Download (ext.)
Purnaprajna, M., Run-time Reconfigurable Cluster of Processors. Proceedings of 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), Workshop on Design, Architecture and Simulation of Chip Multi-Processors, IEEE Computer Society (). , 2008 -
2008 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2289237Realtime multiprocessor for mobile ad hoc networksPUB | PDF | DOI | Download (ext.)
Jungeblut, Thorsten, Realtime multiprocessor for mobile ad hoc networks. Advances in Radio Science 6 (). , 2008 -
2008 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2493966Frequency Estimation and Compensation for Coherent QPSK Transmission with DFB LasersPUB | DOI | Download (ext.)
Hoffmann, Sebastian, Frequency Estimation and Compensation for Coherent QPSK Transmission with DFB Lasers. Proc. OSA Topical Meeting Coherent Optical Technologies and Applications (COTA) (). , 2008 -
2008 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 249409632-krad/s Polarization and 3-dB PDL Tracking in a Realtime Digital Coherent Polarization-Multiplexed QPSK ReceiverPUB | DOI
Pfau, Timo, 32-krad/s Polarization and 3-dB PDL Tracking in a Realtime Digital Coherent Polarization-Multiplexed QPSK Receiver. Proceedings of the 2008 IEEE-LEOS Summer Topical Meetings (). Piscataway, NJ, 2008 -
2008 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2289205Design Space Exploration for Resource Efficient VLIW-ProcessorsPUB
Jungeblut, Thorsten, Design Space Exploration for Resource Efficient VLIW-Processors. University Booth of the Design, Automation and Test in Europe (DATE) conference (). , 2008 -
2008 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2289175Hardware Accelerators for Elliptic Curve CryptographyPUB | PDF | DOI | Download (ext.)
Puttmann, Christoph, Hardware Accelerators for Elliptic Curve Cryptography. Advances in Radio Science 6 (). , 2008 -
2008 | Monographie | Veröffentlicht | PUB-ID: 2493583Selbstoptimierende Systeme des Maschinenbaus – Definitionen, Anwendungen, Konzepte.PUB
Adelt, P., Selbstoptimierende Systeme des Maschinenbaus – Definitionen, Anwendungen, Konzepte.. Band 234 (). Paderborn, 2008 -
2008 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2493684Coherent optical communication: Towards realtime systems at 40 Gbit/s and beyondPUB | DOI | WoS | PubMed | Europe PMC
Pfau, Timo, Coherent optical communication: Towards realtime systems at 40 Gbit/s and beyond. Optics Express 16 (2). , 2008 -
2008 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494113Realtime digital polarization and carrier recovery in a polarization-multiplexed optical QPSK transmissionPUB | DOI
Noe, Reinhold, Realtime digital polarization and carrier recovery in a polarization-multiplexed optical QPSK transmission. Proceedings of the 2008 IEEE/LEOS Summer Topical Meetings (). Piscataway, NJ, 2008 -
2007 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2286362GigaNoC - A Hierarchical Network-on-Chip for Scalable Chip-MultiprocessorsPUB | DOI | Download (ext.)
Puttmann, Christoph, GigaNoC - A Hierarchical Network-on-Chip for Scalable Chip-Multiprocessors. 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007) (). Piscataway, NJ, 2007 -
2007 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472738Design of Homogeneous Communication Infrastructures for Partially Reconfigurable FPGAsPUB | Download (ext.)
Hagemeyer, Jens, Design of Homogeneous Communication Infrastructures for Partially Reconfigurable FPGAs. Proc. of the Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA '07) (). Las Vegas, USA, 2007 -
2007 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494198The Utilization of Reconfigurable Hardware to Implement Digital Controllers: a ReviewPUB | DOI
Paiz, Carlos, The Utilization of Reconfigurable Hardware to Implement Digital Controllers: a Review. Proceedings of the IEEE International Symposium on Industrial Electronics (). , 2007 -
2007 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472729Run-Time Reconfiguration of FPGA-Based Drive ControllersPUB | DOI
Schulz, Bernd, Run-Time Reconfiguration of FPGA-Based Drive Controllers. European Conference on Power Electronics and Applications (EPE 2007) (). Aalborg, Denmark, 2007 -
2007 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472743A Design Methodology for Communication Infrastructures on Partially Reconfigurable FPGASPUB | DOI
Hagemeyer, Jens, A Design Methodology for Communication Infrastructures on Partially Reconfigurable FPGAS. Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL) (). Amsterdam, Netherlands, 2007 -
2007 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472748INDRA – Integrated Design Flow for Reconfigurable ArchitecturesPUB | Download (ext.)
Hagemeyer, Jens, INDRA – Integrated Design Flow for Reconfigurable Architectures. Proceedings of the Conference on Design, Automation and Test in Europe (DATE '07) – University Booth (). , 2007 -
2007 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2289033Compiler-Driven Reconfiguration of MultiprocessorsPUB | PDF | Download (ext.)
Hussmann, Michael, Compiler-Driven Reconfiguration of Multiprocessors. Proceedings of the Workshop on Application Specific Processors (WASP) 2007 (). , 2007 -
2007 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2289057Real-Time Multiprocessor SoC for Mobile Ad Hoc NetworksPUB | Download (ext.)
Jungeblut, Thorsten, Real-Time Multiprocessor SoC for Mobile Ad Hoc Networks. Proceedings of the Conference on Design, Automation and Test in Europe (DATE '07) – University Booth, 2007 (). , 2007 -
2007 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494165A design framework for FPGA-based dynamically reconfigurable digital controllersPUB | DOI
Paiz, Carlos, A design framework for FPGA-based dynamically reconfigurable digital controllers. Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS2007) (). Piscataway, NJ, 2007 -
2007 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494230PDL-Tolerant Real-time Polarization-Multiplexed QPSK Transmission with Digital Coherent Polarization Diversity ReceiverPUB | DOI
Pfau, Timo, PDL-Tolerant Real-time Polarization-Multiplexed QPSK Transmission with Digital Coherent Polarization Diversity Receiver. Proceedings of the 2007 IEEE/LEOS Summer Topical Meetings (). Piscataway, NJ, 2007 -
2007 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494285Polarization-Multiplexed 2.8 Gbit/s Synchronous QPSK Transmission with Real-Time Digital Polarization TrackingPUB | DOI | Download (ext.)
Pfau, Timo, Polarization-Multiplexed 2.8 Gbit/s Synchronous QPSK Transmission with Real-Time Digital Polarization Tracking. Proceedings of ECOC 3 (). , 2007 -
2007 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494514Flexible Hardware Platforms for Dynamic ReconfigurationPUB
Porrmann, Mario, Flexible Hardware Platforms for Dynamic Reconfiguration. Invited Talk at the 2nd Int. Conf. on Industrial and Information Systems (ICIIS 2007), Reconfigurable Computing Workshop (). , 2007 -
2007 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2285993Partial Dynamic Reconfiguration in a Multi-FPGA Clustered Architecture Based on LinuxPUB | DOI
Rana, V., Partial Dynamic Reconfiguration in a Multi-FPGA Clustered Architecture Based on Linux. Proceedings of the 21st International Parallel and Distributed Processing Symposium (IPDPS 2007) - Reconfigurable Architecture Workshop (RAW), IEEE Computer Society. (). Piscataway, NJ, 2007 -
2007 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2493699Coherent Digital Polarization Diversity Receiver for Real-Time Polarization-Multiplexed QPSK Transmission at 2.8 Gb/sPUB | DOI | WoS
Pfau, Timo, Coherent Digital Polarization Diversity Receiver for Real-Time Polarization-Multiplexed QPSK Transmission at 2.8 Gb/s. Photonics Technology Letters, IEEE 19 (24). , 2007 -
2007 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494159Hardware-in-the-Loop Entwicklungsumgebung fuer informationsverarbeitende Komponenten mechatronischer SystemePUB
Pohl, Christopher, Hardware-in-the-Loop Entwicklungsumgebung fuer informationsverarbeitende Komponenten mechatronischer Systeme. 5. Paderborner Workshop Entwurf mechatronischer Systeme (). , 2007 -
2007 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494262Realtime Optical Synchronous QPSK Transmission with DFB lasersPUB | DOI
Pfau, Timo, Realtime Optical Synchronous QPSK Transmission with DFB lasers. Proceedings of the 2007 IEEE/LEOS Summer Topical Meetings (). Piscataway, NJ, 2007 -
2007 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2145016Resource efficiency of the GigaNetIC chip multiprocessor architecturePUB | DOI | WoS
Niemann, Jörg-Christian, Resource efficiency of the GigaNetIC chip multiprocessor architecture. Journal of System Architecture 53 (5-6). , 2007 -
2007 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494202Real-time Digital Carrier & Data Recovery for a Synchronous Optical Quadrature Phase Shift Keying Transmission SystemPUB | DOI
Noe, Reinhold, Real-time Digital Carrier & Data Recovery for a Synchronous Optical Quadrature Phase Shift Keying Transmission System. Proceedings of System Microwave Symposium. IEEE/MTT-S International (). Piscataway, NJ, 2007 -
2007 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494512A Layer-Model Based Methodology for the Design of Dynamically Reconfigurable Systems. Invited TalkPUB
Porrmann, Mario, A Layer-Model Based Methodology for the Design of Dynamically Reconfigurable Systems. Invited Talk. 2nd Int. Conf. on Industrial and Information Systems (ICIIS 2007), Reconfigurable Computing Workshop (). , 2007 -
2007 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2289049A Multiprocessor Cache for Massively Parallel SoC ArchitecturesPUB | DOI
Niemann, Jörg-Christian, A Multiprocessor Cache for Massively Parallel SoC Architectures. ARCS'07: Architecture of Computing Systems 4415 (). Zurich, Switzerland, 2007 -
2007 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2285724Defragmentation Algorithms for Partially Reconfigurable HardwarePUB | DOI
Köster, M., Defragmentation Algorithms for Partially Reconfigurable Hardware. VLSI-SoC: From Systems to Silicon 240 (). , 2007 -
2006 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494328Hardware-Efficient and Phase Noise Tolerant Digital Synchronous QPSK Receiver ConceptPUB | DOI | Download (ext.)
Hoffmann, Sebastian, Hardware-Efficient and Phase Noise Tolerant Digital Synchronous QPSK Receiver Concept. Proceedings Optical Amplifiers and Their Applications/Coherent Optical Technologies and Applications (). , 2006 -
2006 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494326REPLICA2Pro: Task Relocation by Bitstream Manipulation in VIRTEX-II/Pro FPGAsPUB | DOI | Download (ext.)
Kalte, Heiko, REPLICA2Pro: Task Relocation by Bitstream Manipulation in VIRTEX-II/Pro FPGAs. Proceedings of the 3rd Conference on Computing Frontiers (). New York, 2006 -
2006 | Sammelwerksbeitrag | Veröffentlicht | PUB-ID: 2285718Implementation of Self-Organizing Feature Maps in Reconfigurable HardwarePUB | DOI
Porrmann, Mario, Implementation of Self-Organizing Feature Maps in Reconfigurable Hardware. FPGA Implementations of Neural Networks (). Boston, MA, 2006 -
2006 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494321Teaching Reconfigurable Computing Theory and PracticePUB
Porrmann, Mario, Teaching Reconfigurable Computing Theory and Practice. International Workshop on Reconfigurable Computing Education (on CD) (). , 2006 -
2006 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494340Relocation and Defragmentation for Heterogeneous Reconfigurable SystemsPUB
Koester, Markus, Relocation and Defragmentation for Heterogeneous Reconfigurable Systems. Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA '06) (). , 2006 -
2006 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494364A Layer Model for Systematically Designing Dynamically Reconfigurable SystemsPUB | DOI
Kettelhoit, Boris, A Layer Model for Systematically Designing Dynamically Reconfigurable Systems. Proceedings of the 16th International Conference on Field Programmable Logic and Applications (). Piscataway, NJ, 2006 -
2006 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 24943901.6 Gbit/s Real-Time Synchronous QPSK Transmission with Standard DFB LasersPUB | DOI
Pfau, Timo, 1.6 Gbit/s Real-Time Synchronous QPSK Transmission with Standard DFB Lasers. Proceedings of the 32nd European Conference on Optical Communication (ECOC 2006) (). , 2006 -
2006 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2473942Dedicated Module Access in Dynamically Reconfigurable SystemsPUB | DOI
Hagemeyer, Jens, Dedicated Module Access in Dynamically Reconfigurable Systems. Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS) (). Washington, DC, 2006 -
2006 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494374Evaluation of on-chip interfaces for dynamically reconfigurable coprocessorsPUB | DOI
Griese, Björn, Evaluation of on-chip interfaces for dynamically reconfigurable coprocessors. Proceedings of the 5th International Symposium on Parallel Computing in Electrical Engineering (). Los Alamitos, Calif. , 2006 -
2006 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494380Application-driven Development of Concurrent Packet Processing PlatformsPUB | Download (ext.)
Sauer, Christian, Application-driven Development of Concurrent Packet Processing Platforms. Proceedings of the 5th International Symposium on Parallel Computing in Electrical Engineering (). , 2006 -
2006 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494405Dynamically Reconfigurable Hardware for Autonomous Mini-RobotsPUB | DOI
Paiz, Carlos, Dynamically Reconfigurable Hardware for Autonomous Mini-Robots. 32nd Annual Conference of the IEEE Industrial Electronics Society (IECON-2006) (). , 2006 -
2006 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2493726First Real-Time Data Recovery for SynchroneusQPSK Transmission with Standard DFB LasersPUB | DOI | WoS
Pfau, Timo, First Real-Time Data Recovery for SynchroneusQPSK Transmission with Standard DFB Lasers. IEEE PHOTONICS TECHNOLOGY LETTERS 18 (18). , 2006 -
2006 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494368Reconfigurable Hardware in-the-Loop Simulations for Digital Control DesignPUB
Paiz, Carlos, Reconfigurable Hardware in-the-Loop Simulations for Digital Control Design. 3th International Conference on Informatics in Control, Automation and Robotics (ICINCO) (). , 2006 -
2006 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2288961GigaNetIC – A Scalable Embedded On-Chip Multiprocessor Architecture for Network ApplicationsPUB | DOI
Niemann, Jörg-Christian, GigaNetIC – A Scalable Embedded On-Chip Multiprocessor Architecture for Network Applications. ARCS'06 Architecture of Computing Systems 3894 (). Berlin, Heidelberg, 2006 -
2006 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2493754Synchronous QPSK transmission at 1.6 Gbit/s with standard DFB lasers and real-time digital receiverPUB | DOI | WoS
Pfau, Timo, Synchronous QPSK transmission at 1.6 Gbit/s with standard DFB lasers and real-time digital receiver. IEEE Electronic Letters 42 (20). , 2006 -
2006 | Patent | Veröffentlicht | PUB-ID: 2494093Flexible Beschleunigungseinheit für die Verarbeitung von DatenpaketenPUB
Niemann, J.-C., Flexible Beschleunigungseinheit für die Verarbeitung von Datenpaketen. (). , 2006 -
2006 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494346Synchrone 1,6-Gbits-QPSK-Datenübertragung in Echtzeit mit DFB-LasernPUB
Hoffmann, Sebastian, Synchrone 1,6-Gbits-QPSK-Datenübertragung in Echtzeit mit DFB-Lasern. Workshop der ITG Fachgruppe 5.3.1, Modellierung photonischer Komponenten und Systeme (). , 2006 -
2006 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494360A Reconfigurable Ethernet Switch for Self-Optimizing Communication SystemsPUB | DOI
Griese, Björn, A Reconfigurable Ethernet Switch for Self-Optimizing Communication Systems. Proceedings of the IFIP Conference on Biologically Inspired Cooperative Computing (BICC 2006) (). , 2006 -
2006 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2286278Bio-inspired massively parallel architectures for nanotechnologiesPUB | DOI
Jäger, Björn, Bio-inspired massively parallel architectures for nanotechnologies. Proceeding of the IEEE International Symposium on Circuits and Systems (ISCAS 2006). (). Piscataway, NJ, 2006 -
2006 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2288969A Lightweight NoC for the NOVA Packet Processing PlattformPUB | PDF | Download (ext.)
Sauer, Christian, A Lightweight NoC for the NOVA Packet Processing Plattform. Design, Automation and Test in Europe DATE, Future Interconnect and Network-on-Chip (NoC) Workshop (). Munich, Germany, 2006 -
2005 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2288882Adaptable Switch boxes as on-chip routing nodes for networks-on-chipPUB | PDF | DOI | Download (ext.)
Eickhoff, Ralf, Adaptable Switch boxes as on-chip routing nodes for networks-on-chip. From Specification to Embedded Systems Application 184 (). Boston, MA, 2005 -
2005 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494412Component case study of a self-optimizing RCOS/RTOS system. A reconfigurable network servicePUB | DOI | Download (ext.)
Griese, Björn, Component case study of a self-optimizing RCOS/RTOS system. A reconfigurable network service. From Specification to Embedded Systems Application 184 (). Boston, MA, 2005 -
2005 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2288910Technologieplanung in der Mikroelektronik – von Moore's Law zur Nanotechnologie-RoadmapPUB
Liß, Christian, Technologieplanung in der Mikroelektronik – von Moore's Law zur Nanotechnologie-Roadmap. Symposium fuer Vorausschau und Technologieplanung (). Berlin, Germany, 2005 -
2005 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494437Task Placement for Heterogeneous Reconfigurable ArchitecturesPUB | DOI
Koester, Markus, Task Placement for Heterogeneous Reconfigurable Architectures. Proceedings of the IEEE 2005 Conference on Field-Programmable Technology (FPT '05) (). Piscataway, NJ, 2005 -
2005 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494424Context Saving and Restoring for Multitasking in Reconfigurable SystemsPUB | DOI
Kalte, Heiko, Context Saving and Restoring for Multitasking in Reconfigurable Systems. 15th International Conference on Field Programmable Logic and Applications (). Piscataway, NJ, 2005 -
2005 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494429Run-Time Defragmentation for Partially Reconfigurable SystemsPUB
Koester, Markus, Run-Time Defragmentation for Partially Reconfigurable Systems. Proceedings of the International Conference on Very Large Scale Integration (IFIP VLSI-SOC) (). , 2005 -
2005 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2288900Rekonfigurierbare Hardware zur Regelung mechatronischer SystemePUB
Kettelhoit, Boris, Rekonfigurierbare Hardware zur Regelung mechatronischer Systeme. 3. Paderborner Workshop: Intelligente mechatronische Systeme (). , 2005 -
2005 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2286050Placement-Oriented Modeling of Partially Reconfigurable ArchitecturesPUB | Download (ext.)
Koester, M., Placement-Oriented Modeling of Partially Reconfigurable Architectures. Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005) - Reconfigurable Architectures Workshop (RAW), IEEE Computer Society, on CD. (). , 2005 -
2005 | Sammelwerksbeitrag | Veröffentlicht | PUB-ID: 2145286A framework for design space exploration of resource efficient network processing on multiprocessor SoCsPUB | DOI
Grünewald, Matthias, A framework for design space exploration of resource efficient network processing on multiprocessor SoCs. Network Processor Design: Issues and Practices 3 (). , 2005 -
2005 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2288853An Evaluation of the Scalable GigaNetIC Architecture for Access NetworksPUB | PDF
Niemann, Jörg-Christian, An Evaluation of the Scalable GigaNetIC Architecture for Access Networks. Advanced Networking and Communications Hardware Workshop (ANCHOR), held in conjunction with the 32nd Annual International Symposium on Computer Architecture (ISCA 2005) (). , 2005 -
2005 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2288944Dynamically reconfigurable hardware for digital controllers in mechatronic systemsPUB | DOI
Paiz, C., Dynamically reconfigurable hardware for digital controllers in mechatronic systems. IEEE International Conference on Mechatronics (ICM 2005) (). Piscataway, NJ, 2005 -
2005 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2288829Dynamically Reconfigurable Hardware for Self-Optimizing Mechatronic SystemsPUB
Kettelhoit, Boris, Dynamically Reconfigurable Hardware for Self-Optimizing Mechatronic Systems. 5. GMM/ITG/GI-Workshop Multi-Nature Systems (). , 2005 -
2005 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2285654A System Approach for Partially Reconfigurable ArchitecturesPUB | DOI
Kalte, Heiko, A System Approach for Partially Reconfigurable Architectures. International Journal of Embedded Systems (IJES), Inderscience Publisher 1 (3/4). , 2005 -
2005 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2286119REPLICA: A Bitstream Manipulation Filter for Module Relocation in Partial Reconfigurable SystemsPUB | DOI
Kalte, H., REPLICA: A Bitstream Manipulation Filter for Module Relocation in Partial Reconfigurable Systems. Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005) - Reconfigurable Architectures Workshop (RAW), IEEE Computer Society, on CD. (). , 2005 -
2005 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2286309A scalable parallel SoC architecture for network processorsPUB | DOI
Niemann, J.-G., A scalable parallel SoC architecture for network processors. VLSI, 2005. Proceedings. IEEE Computer Society Annual Symposium on (). , 2005 -
2004 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494463Developing an IP-DSLAM Benchmark for Network Processor UnitsPUB
Hagen, Gunnar, Developing an IP-DSLAM Benchmark for Network Processor Units. ANCHOR 2004, Advanced Networking and Communications Hardware Workshop, held in conjunction with the 31st Annual International Symposium on Computer Architecture (ISCA 2004) (). , 2004 -
2004 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2285912Dynamic Reconfiguration of Real-Time Network InterfacesPUB | DOI
Vonnahme, E., Dynamic Reconfiguration of Real-Time Network Interfaces. Parallel Computing in Electrical Engineering, 2004. PARELEC 2004. International Conference on (). Los Alamitos, Calif. , 2004 -
2004 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2288708Leistungsbewertung unterschiedlicher Einbettungsvarianten dynamisch rekonfigurierbarer HardwarePUB
Kalte, Heiko, Leistungsbewertung unterschiedlicher Einbettungsvarianten dynamisch rekonfigurierbarer Hardware. ARCS 2004 – Organic and Pervasive Computing (). , 2004 -
2004 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2288760Dynamische Rekonfiguration echtzeitfähiger NetzwerkschnittstellenPUB
Vonnahme, Erik, Dynamische Rekonfiguration echtzeitfähiger Netzwerkschnittstellen. VDE Kongress 2004 – ITG Fachtagung 'Ambient Intelligence' (Band 1). Berlin, Germany, 2004 -
2004 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2286101A mapping strategy for resource-efficient network processing on multiprocessor SoCsPUB | DOI
Grunewald, M., A mapping strategy for resource-efficient network processing on multiprocessor SoCs. Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings 2 (). Los Alamitos, Calif. , 2004 -
2004 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2286233Study on column wise design compaction for reconfigurable systemsPUB | DOI
Kalte, H., Study on column wise design compaction for reconfigurable systems. Field-Programmable Technology, 2004. Proceedings. 2004 IEEE International Conference on (). Piscataway, NJ, 2004 -
2004 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2288776Parallele Architekturen für NetzwerkprozessorenPUB | Download (ext.)
Niemann, Jörg-Christian, Parallele Architekturen für Netzwerkprozessoren. Ambient Intelligence, VDE Kongress 1 (). , 2004 -
2004 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2288730A Comparative Study on System Approaches for Partially Reconfigurable ArchitecturesPUB
Kalte, Heiko, A Comparative Study on System Approaches for Partially Reconfigurable Architectures. Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA '04) (). Las Vegas, Nevada, USA, 2004 -
2004 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2288742Hardware Support for Dynamic Reconfiguration in Reconfigurable SoC ArchitecturesPUB | DOI
Griese, Björn, Hardware Support for Dynamic Reconfiguration in Reconfigurable SoC Architectures. Proceedings of the 14th International Conference on Field Programmable Logic and its Applications (FPL2004) 3203 (). Antwerp, Belgium, 2004 -
2004 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2286146Network application driven instruction set extensions for embedded processing clustersPUB | DOI
Grunewald, M., Network application driven instruction set extensions for embedded processing clusters. Parallel Computing in Electrical Engineering, 2004. PARELEC 2004. International Conference on (). Los Alamitos, Calif. , 2004 -
2004 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2288700A framework for design space exploration of resource efficient network processing on multiprocessor SoCsPUB
Grünewald, Matthias, A framework for design space exploration of resource efficient network processing on multiprocessor SoCs. Proceedings of the 3rd Workshop on Network Processors & Applications (). Madrid, Spain, 2004 -
2004 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2285942Hardware Accelerated Data AnalysisPUB | DOI
Franzmeier, M., Hardware Accelerated Data Analysis. Parallel Computing in Electrical Engineering, 2004. PARELEC 2004. International Conference on (). Los Alamitos, Calif. , 2004 -
2004 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2286356System-on-programmable-chip approach enabling online fine-grained 1D-placementPUB | DOI
Kalte, H., System-on-programmable-chip approach enabling online fine-grained 1D-placement. Parallel and Distributed Processing Symposium, 2004. Proceedings. 18th International (). , 2004 -
2004 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2286138gNBX - reconfigurable hardware acceleration of self-organizing mapsPUB | DOI
Pohl, C., gNBX - reconfigurable hardware acceleration of self-organizing maps. Field-Programmable Technology, 2004. Proceedings. 2004 IEEE International Conference on (). Piscataway, NJ, 2004 -
2003 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2286024A holistic methodology for network processor designPUB | DOI
Bonorden, O., A holistic methodology for network processor design. Local Computer Networks, 2003. LCN '03. Proceedings. 28th Annual IEEE International Conference on (). , 2003 -
2003 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2145324A Massively Parallel Architecture for Self-Organizing Feature MapsPUB | DOI | WoS | PubMed | Europe PMC
Porrmann, Mario, A Massively Parallel Architecture for Self-Organizing Feature Maps. IEEE Transactions on Neural Networks, Special Issue on Hardware Implementations 14 (5). , 2003 -
2002 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2288575A Prototyping Platform for Dynamically Reconfigurable System on Chip DesignsPUB
Kalte, Heiko, A Prototyping Platform for Dynamically Reconfigurable System on Chip Designs. Proceedings of the IEEE Workshop Heterogeneous reconfigurable Systems on Chip (SoC) (). Hamburg, Germany, 2002 -
2002 | Monographie | Veröffentlicht | PUB-ID: 2493620Leistungsbewertung eingebetteter Neurocomputersysteme. Dissertation.PUB
Porrmann, Mario, Leistungsbewertung eingebetteter Neurocomputersysteme. Dissertation.. 104 (). Paderborn, 2002 -
2002 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2288603A Reconfigurable SOM Hardware AcceleratorPUB | PDF
Porrmann, Mario, A Reconfigurable SOM Hardware Accelerator. (). , 2002 -
2002 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2288565Implementation of a RISC Processor Core for SoC Designs – FPGA Prototype vs. ASIC ImplementationPUB | PDF
Langen, Dominik, Implementation of a RISC Processor Core for SoC Designs – FPGA Prototype vs. ASIC Implementation. Proceedings of the IEEE-Workshop: Heterogeneous reconfigurable Systems on Chip (SoC) (). Hamburg, Germany, 2002 -
2002 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2288589Dynamically Reconfigurable Hardware – A New Perspective for Neural Network ImplementationsPUB | DOI
Porrmann, Mario, Dynamically Reconfigurable Hardware – A New Perspective for Neural Network Implementations. Proceedings of the International Conference on Field Programmable Logic and Applications (FPL2002) 2438 (). Montpellier, France, 2002 -
2002 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2285896Implementation of artificial neural networks on a reconfigurable hardware acceleratorPUB | DOI
Porrmann, Mario, Implementation of artificial neural networks on a reconfigurable hardware accelerator. Parallel, Distributed and Network-based Processing, 2002. Proceedings. 10th Euromicro Workshop on (). , 2002 -
2002 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2285966On-chip interconnects for next generation system-on-chipsPUB | DOI
Brinkmann, A., On-chip interconnects for next generation system-on-chips. ASIC/SOC Conference, 2002. 15th Annual IEEE International (). , 2002 -
2001 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2288549The Impact of Communication on Hardware Accelerators for Neural NetworksPUB
Porrmann, Mario, The Impact of Communication on Hardware Accelerators for Neural Networks. Proceedings of The 5th World Multi-Conference on Systemics, Cybernetics and Informatics (SCI) 3 (). Orlando, Florida, USA, 2001 -
2001 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2288555Extension Module for Application-Specific Hardware on the Minirobot KheperaPUB | PDF
Niemann, Jörg-Christian, Extension Module for Application-Specific Hardware on the Minirobot Khepera. Autonomous Minirobots for Research and Edutainment (AMiRE 2001) (). Paderborn, Germany, 2001 -
2001 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2288526XipChip – A Multiprocessor CPU for Multifunction PeripheralsPUB
Porrmann, Mario, XipChip – A Multiprocessor CPU for Multifunction Peripherals. Proceedings of The 5th World Multi-Conference on Systemics, Cybernetics and Informatics (SCI) 15 (). Orlando, Florida, USA, 2001 -
2001 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2288539A Dynamically Reconfigurable Hardware Accelerator for Self-Organizing Feature MapsPUB
Porrmann, Mario, A Dynamically Reconfigurable Hardware Accelerator for Self-Organizing Feature Maps. Proceedings of The 5th World Multi-Conference on Systemics, Cybernetics and Informatics, SCI 2001 3 (). Orlando, Florida, USA, 2001 -
2000 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2286566Rapid Prototyping System für dynamisch rekonfigurierbare HardwarestrukturenPUB
Kalte, Heiko, Rapid Prototyping System für dynamisch rekonfigurierbare Hardwarestrukturen. Workshop: Architekturentwurf und Entwicklung eingebetteter Systeme (AES2000) (). Karlsruhe, Germany, 2000 -
2000 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2286572Using a Dynamically Reconfigurable System to Accelerate Octree Based 3D GraphicsPUB
Kalte, Heiko, Using a Dynamically Reconfigurable System to Accelerate Octree Based 3D Graphics. Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA´2000) 5 (). Monte Carlo Resort, Las Vegas, Nevada, USA, 2000 -
1999 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2286315SOM hardware with acceleration module for graphical representation of the learning processPUB | DOI
Porrmann, Mario, SOM hardware with acceleration module for graphical representation of the learning process. Microelectronics for Neural, Fuzzy and Bio-Inspired Systems, 1999. MicroNeuro '99. Proceedings of the Seventh International Conference on (). , 1999 -
1998 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2286468A Hybrid Knowledge Processing SystemPUB
Porrmann, Mario, A Hybrid Knowledge Processing System. Proceedings of the Conference Neural Networks and their Applications (NEURAP) (). Marseille, France, 1998 -
1998 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2285592SOM Accelerator SystemPUB | Download (ext.)
Rüping, Stefan, SOM Accelerator System. Neurocomputing 21 (). , 1998 -
1997 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2286384A High Performance SOFM Hardware-SystemPUB | PDF | Download (ext.)
Rüping, Stefan, A High Performance SOFM Hardware-System. Proceedings of the International Work-Conference on Artificial and Natural Neural Networks (IWANN´97) (). Lanzarote, Spain, 1997 -
1997 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2286402SOM Hardware-AcceleratorPUB | PDF | Download (ext.)
Rüping, Stefan, SOM Hardware-Accelerator. Workshop on Self-Organizing Maps (WSOM) (1997). Espoo, Finnland, 1997 -
1997 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2286241HIBRIC-MEM, a Memory Controller for PowerPC Based SystemsPUB | DOI
Porrmann, Mario, HIBRIC-MEM, a Memory Controller for PowerPC Based Systems. Proceedings of the 23rd EUROMICRO Conference (). Budapest, Ungarn, 1997 -
1996 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2285575Neuronale AssoziativspeicherPUB
Palm, Günther, Neuronale Assoziativspeicher. Neuroinformatik Statusseminar (). , 1996