222 Publikationen
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2019 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2933490
C. Lian Sang, et al., “Numerical and Experimental Evaluation of Error Estimation for Two-Way Ranging Methods”, Sensors, vol. 19, 2019, : 616.PUB | PDF | DOI | Download (ext.) | WoS | PubMed | Europe PMC -
2019 | Datenpublikation | PUB-ID: 2939390
C. Lian Sang, et al., Supplementary Experimental Data for the Paper entitled Numerical and Experimental Evaluation of Error Estimation for Two-Way Ranging Methods, Bielefeld University, 2019.PUB | Dateien verfügbar | DOI
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2019 | Sammelwerksbeitrag | Veröffentlicht | PUB-ID: 2920469A. Oleksiak, et al., “M2DC – A Novel Heterogeneous Hyperscale Microserver Platform”, Hardware Accelerators in Data Centers, C. Kachris, B. Falsafi, and D. Soudris, eds., 1st ed., Cham, Switzerland: Springer International Publishing AG, 2019, pp.109-128.PUB | DOI
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2018 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2982045A. Cristal, et al., “LEGaTO. First steps towards energy-efficient toolset for heterogeneous computing”, SAMOS '18. Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, New York, NY: ACM, 2018, pp.210-217.PUB | DOI
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2018 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2979448A. Cristal, et al., “LEGaTO. First steps towards energy-efficient toolset for heterogeneous computing”, Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, T. Mudge, ed., New York, NY, USA: ACM, 2018, pp.210-217.PUB | DOI
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2018 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2955564A. Cristal, et al., “LEGaTO Project: Towards Energy-Efficient, Secure, Fault-tolerant Toolset for Heterogeneous Computing.”, Proceedings of the 15th ACM International Conference on Computing Frontiers, D. Kaeli, ed., New York, NY: ACM, 2018, pp.276-278.PUB | DOI | Download (ext.)
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2018 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2940681D. Klimeck, et al., “Resource-efficient Reconfigurable Computer-on-Module for Embedded Vision Applications”, 2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP), Piscataway, NJ: IEEE, 2018.PUB | DOI
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2018 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2921313
C. Lian Sang, et al., “An Analytical Study of Time of Flight Error Estimation in Two-Way Ranging Methods”, 2018 International Conference on Indoor Positioning and Indoor Navigation (IPIN), Piscataway, NJ: IEEE, 2018.PUB | PDF | DOI | Download (ext.)
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2018 | Datenpublikation | PUB-ID: 2919795
C. Lian Sang, et al., Supplementary Data for the Paper entitled ''An Analytical Study of Time of Flight Error Estimation in Two-Way Ranging Methods'', Bielefeld University, 2018.PUB | Dateien verfügbar | DOI
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2018 | Kurzbeitrag Konferenz / Poster | Veröffentlicht | PUB-ID: 2918788
M. Kaiser, et al., “Accelerating Hamming Distance Comparisons for Locality Sensitive Hashing (LSH) using FPGAs”, 12th CeBiTec Symposium - Big Data in Medicine and Biotechnology - Abstract Book, vol. 12, Bielefeld: 2018, pp.48-49.PUB | PDF
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2018 | Konferenzbeitrag | PUB-ID: 2921315C. Klarhorst, et al., “Development of Energy Models for Design Space Exploration of Embedded Many-Core Systems”, Presented at the 6th International Workshop on High Performance Energy Efficient Embedded Systems (HIP3ES 2018), Manchester, United Kingdom, 2018.PUB
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2017 | Sammelwerksbeitrag | Veröffentlicht | PUB-ID: 2908972G. Sievers, et al., “The CoreVA-MPSoC: A Multiprocessor Platform for Software-Defined Radio”, Computing Platforms for Software-Defined Radio, W. Hussain, et al., eds., Cham, Switzerland: Springer International Publishing, 2017, pp.29--59.PUB | DOI
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2017 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2937407G. Agosta, et al., “The M2DC Approach towards Resource-efficient Computing”, OPPORTUNITIES AND CHALLENGES for European Projects. Volume 1: EPS Portugal 2017/2018, A. Bagnato, et al., eds., Setúbal, Portugal: SCITEPRESS, 2017, pp.150-176.PUB | DOI
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2017 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2909430A. Irwansyah, et al., “FPGA-based Multi-Robot Tracking”, Journal of Parallel and Distributed Computing, vol. 107, 2017, pp. 146-161.PUB | DOI | Download (ext.) | WoS
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2017 | Kurzbeitrag Konferenz / Poster | Veröffentlicht | PUB-ID: 2918683
M. Kaiser, et al., “A Reconfigurable Heterogeneous Microserver Architecture for Energy-efficient Computing”, Third International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC'17), Denver, CO: 2017.PUB | PDF | Download (ext.)
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2017 | Konferenzbeitrag | Angenommen | PUB-ID: 2912816J. Ax, et al., “Comparing synchronous, mesochronous and asynchronous NoCs for GALS based MPSoC”, IEEE 11th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-17), Accepted.PUB
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2017 | Konferenzbeitrag | PUB-ID: 2909584A. Oleksiak, et al., “M2DC: Modular Microserver Datacentre with Heterogeneous Hardware”, Presented at the Energy-efficient Servers for Cloud and Edge Computing 2017 Workshop (ENeSCE 2017) - co-located with HiPEAC 2017, Stockholm, Sweden, 2017.PUB
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2017 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2909044J. Lachmair, et al., “From CPU to FPGA – Acceleration of Self-Organizing Maps for Data Mining”, International Joint Conference on Neural Networks (IJCNN 2017), 2017, pp.4299-4308.PUB
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2016 | Kurzbeitrag Konferenz / Poster | PUB-ID: 2909602R. Griessl, et al., “FiPS and M2DC: Novel Architectures for Reconfigurable Hyperscale Servers”, Presented at the Workshop "Reconfigurable Computing — From Embedded Systems to Reconfigurable Hyperscale Servers" co-located with the International Conference on Field-Programmable Logic and Applications (FPL 2016), Lausanne, Switzerland, 2016.PUB | Download (ext.)
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2015 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2732427G. Sievers, et al., “Evaluation of Interconnect Fabrics for an Embedded MPSoC in 28 nm FD-SOI”, 2015 IEEE International Symposium on Circuits & Systems (ISCAS), IEEE, 2015, pp.1925-1928.PUB | DOI | Download (ext.)
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2015 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2901107O.W. Ibraheem, et al., “A resource-efficient multi-camera GigE vision IP core for embedded vision processing platforms”, 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), M. Hübner, M. Gokhale, and R. Cumplido, eds., Piscataway, NJ: IEEE, 2015, pp.1-6.PUB | DOI
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2015 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2901108A. Irwansyah, et al., “FPGA-based circular hough transform with graph clustering for vision-based multi-robot tracking”, 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), M. Hübner, M. Gokhale, and R. Cumplido, eds., Piscataway, NJ: IEEE, 2015, pp.1-8.PUB | DOI
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2015 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2732419A. Buda, et al., “Automatische Protokollanpassung von Echtzeit-Ethernet-Standards durch FPGA-Technologien”, Presented at the Automation 2015, Baden-Baden, 2015.PUB
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2015 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2732431S. Herbrechtsmeier, T. Jungeblut, and M. Porrmann, “Datenflussmodellierung als Methode zur Optimierung von Entwicklungsprozessen am Beispiel der Leiterplattenentwicklung”, Entwurf mechatronischer Systeme, vol. 343, Paderborn: HNI Verlagsschriftenreihe, 2015.PUB
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2015 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2902039
R. Griessl, et al., “FPGA-accelerated Heterogeneous Hyperscale Server Architecture for Next-Generation Compute Clusters”, Presented at the First International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC‘15), held in conjunction with Supercomputing 2015, Austin Texas, USA, 2015.PUB | PDF
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2014 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2698992A. Irwansyah, et al., “FPGA-based Generic Architecture for Rapid Prototyping of Video Hardware Accelerators using NoC AXI4-Stream Interconnect and GigE Vision Camera Interfaces”, Presented at the Bildverarbeitung in der Automation (BVAu) 2014, Lemgo, Germany, 2014.PUB
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2014 | Sammelwerksbeitrag | Veröffentlicht | PUB-ID: 2732400J. Gausemeier, et al., “Development of Self-Optimizing Systems”, Design Methodology for Intelligent Technical Systems. Develop Intelligent Technical Systems of the Future, J. Gausemeier, F.J. Rammig, and W. Schäfer, eds., Lecture Notes in Mechanical Engineering, Berlin Heidelberg: Springer Verlag, 2014, pp.65-117.PUB | DOI
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2014 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2681323D. Sabena, et al., “Reconfigurable High Performance Architectures: How much are they ready for safety-critical applications”, Proceedings of 19th IEEE European Test Symposium (ETS), IEEE, 2014, pp.175-182.PUB | DOI | Download (ext.)
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2014 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2698994M. Walter, et al., “Dynamische Rekonfiguration von Echtzeit-Ethernet-Standards mit harten Echtzeitanforderungen”, Presented at the Kommunikation in der Automation – KommA 2014, Lemgo, Germany, 2014.PUB | Download (ext.)
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2014 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2698999D. Sorrenti, et al., “Exploiting Dynamic Partial Reconfiguration for On-Line On-Demand Testing of Permanent Faults in Reconfigurable Systems”, Presented at the 17th IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Amsterdam, The Netherlands, 2014.PUB | DOI | Download (ext.)
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2014 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2699005D. Cozzi, et al., “AXI-based SpaceFibre IP CORE Implementation”, Presented at the 6th International SpaceWire Conference, Athens, Greece, 2014.PUB | DOI | Download (ext.)
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2014 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2698930R. Griessl, et al., “A Scalable Server Architecture for Next-Generation Heterogeneous Compute Clusters”, Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, EUC 2014, IEEE, 2014, pp.146-153.PUB | DOI | Download (ext.)
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2014 | Konferenzbeitrag | PUB-ID: 2681362L. Cassano, et al., “An Inter-Processor Communication Interface for Data-Flow Centric Heterogeneous Embedded Multiprocessor Systems”, Presented at the DTIS 2014, 9th International conference on Design & Technology of Integrated Systems in Nanoscale Era, Santorini , Greece, 2014.PUB | DOI | Download (ext.)
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2014 | Sammelwerksbeitrag | Veröffentlicht | PUB-ID: 2732260A. Seifried, et al., “Methods of Improving the Dependability of Self-optimizing Systems”, Dependability of Self-Optimizing Mechatronic Systems, J. Gausemeier, et al., eds., Lecture Notes in Mechanical Engineering, Berlin Heidelberg: Springer Verlag, 2014, pp.37-171.PUB | DOI
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2014 | Sammelwerksbeitrag | Veröffentlicht | PUB-ID: 2920470M. Dellnitz, et al., “The Paradigm of Self-optimization”, Design Methodology for Intelligent Technical Systems – Develop Intelligent Technical Systems of the Future, J. Gausemeier, F.-J. Rammig, and W. Schäfer, eds., Lecture notes in mechanical engineering, Berlin Heidelberg: Springer, 2014, pp.1-25.PUB | DOI
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2013 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2576115
S. Korf, et al., “Dynamisch rekonfigurierbare Hardware als Basistechnologie für intelligente technische Systeme”, Proceedings Wissenschaftsforum 2013 Intelligente Technische Systeme, J. Gausemeier, et al., eds., HNI-Verlagsschriftenreihe, vol. 310, Paderborn: Heinz-Nixdorf-Inst., Univ. Paderborn, 2013, pp.79-90.PUB | PDF
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2013 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2634649P. Christ, et al., “Pareto-optimal Signal Processing on Low-Power Microprocessors”, Proceedings of the 12th IEEE International Conference on SENSORS, IEEE, 2013, pp.1843-1846.PUB | DOI | Download (ext.)
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2013 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2681289M. Desogus, et al., “Hardening Dynamically Reconfigurable Processing Modules Architectures: A Neutron Test Experience”, RADECS proceedings, vol. 2, IEEE / Institute of Electrical and Electronics Engineers, 2013, pp.13-16.PUB
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2013 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2681304L. Sterpone, et al., “Dynamic neutron testing of Dynamically Reconfigurable Processing Modules architecture”, Adaptive Hardware and Systems (AHS), 2013 NASA/ESA Conference on, IEEE, 2013, pp.184-188.PUB | DOI | Download (ext.)
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2013 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2634614T. Jungeblut, et al., “A Systematic Approach for Optimized Bypass Configurations for Application-specific Embedded Processors”, ACM Trans. Embed. Comput. Syst., vol. 13, 2013, pp. 1-25.PUB | DOI | Download (ext.) | WoS
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2013 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2575531J. Lachmair, et al., “A reconfigurable neuroprocessor for self-organizing feature maps”, Neurocomputing, vol. 112, 2013, pp. 189-199.PUB | DOI | Download (ext.) | WoS
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2012 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2493811J. Lachmair, et al., “gNBXe - a Reconfigurable Neuroprocessor for Various Types of Self-Organizing Maps”, European Symposium on Artificial Neural Networks, Computational Intelligence and Machine Learning, 2012, pp.645-650.PUB | Download (ext.)
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2012 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2475063S. Lütkemeier, et al., “A 200mV 32b Subthreshold Processor with Adaptive Supply Voltage Control”, Proc. of the International Solid-State Circuits Conference (ISSCC), Institute of Electrical and Electronics Engineers, ed., Piscataway, NJ: IEEE, 2012, pp.484-485.PUB | DOI
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2012 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2517354J. Hagemeyer, et al., “A Scalable Platform for Run-time Reconfigurable Satellite Payload Processing”, 2012 NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2012), Piscataway, NJ: IEEE, 2012, pp.9-16.PUB | DOI | Download (ext.)
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2012 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2493814G. Durelli, et al., “Mini-Robot's Performance Optimization via Online Reconfiguration and HW/SW Task Scheduling.”, 19th Reconfigurable Architectures Workshop (RAW 2012), 2012.PUB | DOI | Download (ext.)
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2012 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2493813T. Jungeblut, et al., “A TCMS-based architecture for GALS NoCs.”, 2012 IEEE International Symposium on Circuits and Systems, IEEE Circuits and Systems Society and Institute of Electrical and Electronics Engineers, eds., Piscataway, NJ: IEEE, 2012.PUB | DOI
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2011 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2286173S. Korf, et al., “Automatic HDL-Based Generation of Homogeneous Hard Macros for FPGAs”, IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2011 : 1 - 3 May 2011, Salt Lake City, Utah, USA ; proceedings , P. Chow, ed., Piscataway, NJ: IEEE, 2011, pp.125-132.PUB | DOI | Download (ext.)
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2011 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2493823M. Grawinkel, et al., “Evaluation of Applied Intra-Disk Redundancy Schemes to Improve Single Disk Reliability.”, MASCOTS2011 The 19th Annual Meeting of the IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems., Association for Computing Machinery, Institute of Electrical and Electronics Engineers, and Nanyang Technological University, eds., Piscataway, NJ: IEEE, 2011, pp.297-306.PUB | DOI | Download (ext.)
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2011 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2493819L. Sterpone, et al., “Analysis of SEU Effects in Partially Reconfigurable SoPCs.”, Proceedings of NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2011), European Space Agency, et al., eds., Piscataway, NJ: IEEE, 2011, pp.129-136.PUB | DOI
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2011 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494507J. Romoth, et al., “Fast Design-space Exploration with FPGA Cluster”, DATE 2011 Workshop on Design Methods and Tools for FPGA-Based Acceleration of Scientific Computing, 2011.PUB | Download (ext.)
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2011 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2476993
T. Jungeblut, et al., “Resource Efficiency of Scalable Processor Architectures for SDR-based Applications (Invited)”, Proc. of the Radar, Communication and Measurement Conference (RADCOM), 2011.PUB | Dateien verfügbar
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2011 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494510R. Griessl, et al., “A Low-Power Vision Processing Platform for Mobile Robots”, Proceedings of the FPL2011 Workshop on Computer Vision on Low-Power Reconfigurable Architectures, 2011.PUB | Download (ext.)
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2011 | Kurzbeitrag Konferenz / Poster | Veröffentlicht | PUB-ID: 2494497M. Köster, et al., “Design Flow for a Fault-Tolerant Reconfigurable Multi-FPGA Architecture for Space Applications”, DATE 2011 Workshop on Design Methods and Tools for FPGA-Based Acceleration of Scientific Computing, 2011.PUB
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2011 | Sammelwerksbeitrag | Veröffentlicht | PUB-ID: 2018536T. Jungeblut, et al., “Design-space Exploration for Flexible WLAN Hardware”, Cross Layer Designs in WLAN Systems, N. Zorba, C. Skianis, and C. Verikoukis, eds., Leicester, UK: Troubador Publishing, 2011, pp.521-564.PUB
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2010 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2493826F. Dittmann, et al., “Implementation of a Dynamically Reconfigurable Processing Module for SpaceWire Networks.”, Proceedings of the International SpaceWire Conference 2010, 2010, pp.193-196.PUB | Download (ext.)
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2010 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472693
M. Porrmann, et al., “RAPTOR – A Scalable Platform for Rapid Prototyping and FPGA-based Cluster Computing”, Parallel Computing: From Multicores and GPU's to Petascale, Advances in Parallel Computing, vol. 19, IOS press, 2010, pp.592-599.PUB | PDF
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2010 | Patent | Veröffentlicht | PUB-ID: 2494087W. Christmann, et al., “Mehrprozessor-Computersystem”, 2010.PUB
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2010 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2286622C. Puttmann, M. Porrmann, and U. Rückert, “Extending GigaNoC towards a Dependable Network-on-Chip”, Digest of the DAC Workshop on Diagnostic Services in Network-on-Chips (DSNOC), 2010.PUB
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2010 | Konferenzbeitrag | PUB-ID: 2286616T. Jungeblut, et al., “A Framework for the Design Space Exploration of Software-Defined Radio Applications”, 2nd International ICST Conference on Mobile Lightweight Wireless Systems, 2010.PUB | Download (ext.)
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2010 | Konferenzbeitrag | PUB-ID: 2286628
T. Jungeblut, et al., “A modular design flow for very large design space explorations”, CDNLive! EMEA 2010, 2010.PUB | Dateien verfügbar
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2010 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2018541
T. Jungeblut, et al., “Resource Efficiency of Hardware Extensions of a 4-issue VLIW Processor for Elliptic Curve Cryptography”, Advances in Radio Science, vol. 8, 2010, pp. 295-305.PUB | PDF | DOI | Download (ext.)
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2009 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2493628C. Pohl, C. Paiz, and M. Porrmann, “vMAGIC - Automatic Code Generation for VHDL”, International Journal of Reconfigurable Computing, Hindawi Publishing Corporation,, vol. 2009, 2009, pp. 1-9.PUB | DOI | Download (ext.)
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2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2493880M. Porrmann, M. Purnaprajna, and C. Puttmann, “Self-optimization of MPSoCs Targeting Resource Efficiency and Fault Tolerance”, NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2009), European Space Agency, Jet Propulsion Laboratory, and The University of Edinburgh, eds., Piscataway, NJ: IEEE, 2009, pp.467-473.PUB | DOI
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2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472673M. Koester, et al., “Design Optimizations to Improve Placeability of Partial Reconfiguration Modules”, Proceedings of the International Conference on Design, Automation and Test in Europe (DATE 2009), European Design Automation Association, ed., Piscataway, NJ: ACM Press, 2009.PUB | DOI | Download (ext.)
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2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472678M. Porrmann, et al., “Rapid Prototyping of Next-Generation Multiprocessor SoCs”, Proceedings of Semiconductor Conference Dresden, SCD 2009, Dresden, Germany: 2009.PUB
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2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472686P.R. Grassi, et al., “SiLLis: A Simplified Language for Monitoring and Debugging of Reconfigurable Systems”, Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA '09), Las Vegas, USA: 2009, pp.174-180.PUB
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2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2493870P.R. Grassi, et al., “A High Level Methodology for Monitoring Network-on-Chips”, Diagnostic Services in Network-on-Chips (DSNOC 2009), Workshop at Design, Automation and Test in Europe., 2009.PUB
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2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2144752
M. Purnaprajna, et al., “Using Run-time Reconfiguration for Energy Savings in Parallel Data Processing”, Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'09, July 13-16, 2009, Las Vegas, Nevada, USA, 2009, pp.119-125.PUB | PDF
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2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2144757R. Dreesen, et al., “A Synchronization Method for Register Traces of Pipelined Processors”, Proceedings of the International Embedded Systems Symposium 2009 (IESS '09), Schloss Langenargen, Germany: 2009, pp.207-217.PUB | Download (ext.)
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2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2144891C. Paiz, et al., “FPGA-in-the-Loop-Simulations for Dynamically Reconfigurable Applications”, Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT'09), IEEE Circuits and Systems Society, IEEE Electron Devices Society, and Institute of Electrical and Electronics Engineers, eds., The University of New South Wales, Sydney, Australia, 9-11, Sydney, Australia: IEEE, 2009, pp.372-375.PUB | DOI
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2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2144772C. Liß, M. Porrmann, and U. Rückert, “InCyte ChipEstimator in Research and Education”, CDNLive EMEA 2009, 2009.PUB
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2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2144830T. Jungeblut, et al., “Design Space Exploration for Next Generation Wireless Technologies (invited talk).”, Proc. of the Electrical and Electronic Engineering for Communication Conference (EEEfCOM) 2009, 2009.PUB
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2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2144880C. Pohl, et al., “Using a Reconfigurable Compute Cluster for the Acceleration of Neural Networks”, Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT '09), IEEE Circuits and Systems Society, IEEE Electron Devices Society, and Institute of Electrical and Electronics Engineers, eds., Sydney, Australia: IEEE, 2009, pp.368-371.PUB | DOI
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2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2493855T. Pfau, et al., “Towards Real-Time Implementation of Coherent Optical Communication”, Proceedings of OFC/NFOEC 2009, Institute of Electrical and Electronics Engineers and Optical Society of America, eds., Piscataway, NJ: OSA, 2009.PUB | DOI
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2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494485C. Pohl, R. Fuest, and M. Porrmann, “Manageable Dynamic Reconfiguration with EVE – Extendable VHDL Editor”, Design Automation and Test in Europe (DATE), University Booth, 2009.PUB | Download (ext.)
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2009 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2144870M. Purnaprajna, M. Porrmann, and U. Rückert, “Run-time reconfigurability in embedded multiprocessors”, ACM SIGARCH Computer Architecture News, vol. 37, 2009, pp. 30-37.PUB | DOI | Download (ext.)
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2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2144782C. Liß, M. Porrmann, and U. Rückert, “Early Exploration of Network Processor Architectures Using Cadence InCyte Chip Estimator”, CDNLive EMEA 2009, 2009.PUB
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2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2144843
C. Paiz, et al., “FPGA-Based Realization of Self-Optimizing Drive-Controllers”, the 35th Annual Conference of the IEEE Industrial Electronics Society (IECON 2009), IEEE Industrial Electronics Society, et al., eds., Piscataway, NJ: IEEE, 2009, pp.2868-2873.PUB | PDF | DOI | Download (ext.)
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2008 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2493929M. Purnaprajna, C. Puttmann, and M. Porrmann, “Power Aware Reconfigurable Multiprocessor for Elliptic Curve Cryptography”, Proceedings of DATE '08: Design, Automation and Test in Europe, ACM, 2008, pp.1462-1467.PUB | DOI | Download (ext.)
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2008 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494491C. Pohl, C. Paiz, and M. Porrmann, “A Hardware-in-the-Loop Design Environment for FPGAs”, Design, Automation and Test in Europe (DATE), University Booth, 2008.PUB
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2008 | Sammelwerksbeitrag | Veröffentlicht | PUB-ID: 2493607C. Paiz, C. Pohl, and M. Porrmann, “Hardware-in-the-Loop Simulations for FPGA-Based Digital Control Design.”, Informatics in Control, Automation and Robotics, J. Andrade-Cetto, et al., eds., vol. 3, Berlin, Heidelberg: Springer-Verlag, 2008, pp.355-372.PUB | DOI
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2008 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2493900T. Pfau, et al., “Ultra-Fast Adaptive Digital Polarization Control in a Realtime Coherent Polarization-Multiplexed QPSK Receiver”, Proceedings of OFC/NFOEC 2008, 2008.PUB | Download (ext.)
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2008 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2493890E. Münch, et al., “FPGA-in-the-Loop Simulations with CAMEL-View”, Self-optimizing Mechatronic Systems: Design the Future, 7th International Heinz Nixdorf Symposium., 2008, pp.429-445.PUB
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2008 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2493939C. Puttmann, J. Shokrollahi, and M. Porrmann, “Resource Efficiency of Instruction Set Extensions for Elliptic Curve Cryptography”, Proceedings of the 5th Internation Conference on Information Technology: New Generations, ITNG 2008, IEEE Computer Society and Institute of Electrical and Electronics Engineers, eds., Piscataway, NJ: IEEE, 2008, pp.131-136.PUB | DOI
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2008 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2493960C. Pohl, C. Paiz, and M. Porrmann, “vMAGIC – VHDL Manipulation and Automation for Reliable System Development”, Proceedings of the 3rd International Workshop on Reconfigurable Computing Education (on CD), 2008.PUB
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2008 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472725J. Hagemeyer, M. Koester, and M. Porrmann, “Hardware Virtualization Exploiting Dynamically Reconfigurable Architectures”, 1. GI/ITG KuVS Fachgespräch Virtualisierung, Heinz Nixdorf Institut, Universität Paderborn, 2008.PUB
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2008 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2493945B. Griese, A. Brinkmann, and M. Porrmann, “SelfS – A Real-Time Protocol for Virtual Ring Topologies”, Proceedings of the 16th International Workshop on Parallel and Distributed Real-Time Systems (WPDRTS '08), on CD, IEEE Computer Society. Technical Committee on Parallel Processing and Institute of Electrical and Electronics Engineers. Technical Committee on Parallel Processing, eds., Piscataway, NJ: IEEE, 2008.PUB | DOI
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2008 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2493957M. Purnaprajna and M. Porrmann, “Run-time Reconfigurable Multiprocessors”, Proceedings of the 22nd International Parallel and Distributed Processing Symposium (IPDPS 2008), PhD Forum, 2008.PUB
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2008 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494157M. Purnaprajna and M. Porrmann, “Run-time Reconfigurable Cluster of Processors”, Proceedings of 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), Workshop on Design, Architecture and Simulation of Chip Multi-Processors, IEEE Computer Society, 2008.PUB | Download (ext.)
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2008 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2289237
T. Jungeblut, et al., “Realtime multiprocessor for mobile ad hoc networks”, Advances in Radio Science, vol. 6, 2008, pp. 239-243.PUB | PDF | DOI | Download (ext.)
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2008 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2493966S. Hoffmann, et al., “Frequency Estimation and Compensation for Coherent QPSK Transmission with DFB Lasers”, Proc. OSA Topical Meeting Coherent Optical Technologies and Applications (COTA), OSA, 2008.PUB | DOI | Download (ext.)
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2008 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494096T. Pfau, et al., “32-krad/s Polarization and 3-dB PDL Tracking in a Realtime Digital Coherent Polarization-Multiplexed QPSK Receiver”, Proceedings of the 2008 IEEE-LEOS Summer Topical Meetings, IEEE Lasers and Electro-Optics Society, ed., Piscataway, NJ: IEEE, 2008, pp.105-106.PUB | DOI
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2008 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2289205T. Jungeblut, et al., “Design Space Exploration for Resource Efficient VLIW-Processors”, University Booth of the Design, Automation and Test in Europe (DATE) conference, 2008.PUB
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2008 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2289175
C. Puttmann, et al., “Hardware Accelerators for Elliptic Curve Cryptography”, Advances in Radio Science, vol. 6, 2008, pp. 259-264.PUB | PDF | DOI | Download (ext.)
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2008 | Monographie | Veröffentlicht | PUB-ID: 2493583P. Adelt, et al., Selbstoptimierende Systeme des Maschinenbaus – Definitionen, Anwendungen, Konzepte., vol. Band 234, HNI-Verlagsschriftenreihe, 2008.PUB
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2008 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2493684T. Pfau, et al., “Coherent optical communication: Towards realtime systems at 40 Gbit/s and beyond”, Optics Express, vol. 16, 2008, pp. 866-872.PUB | DOI | WoS | PubMed | Europe PMC
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2008 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494113R. Noe, et al., “Realtime digital polarization and carrier recovery in a polarization-multiplexed optical QPSK transmission”, Proceedings of the 2008 IEEE/LEOS Summer Topical Meetings, IEEE Lasers and Electro-Optics Society, ed., Piscataway, NJ: IEEE, 2008, pp.99-100.PUB | DOI
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2007 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2286362C. Puttmann, et al., “GigaNoC - A Hierarchical Network-on-Chip for Scalable Chip-Multiprocessors”, 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007), Piscataway, NJ: IEEE, 2007, pp.495-502.PUB | DOI | Download (ext.)
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2007 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472738J. Hagemeyer, et al., “Design of Homogeneous Communication Infrastructures for Partially Reconfigurable FPGAs”, Proc. of the Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA '07), Las Vegas, USA: 2007.PUB | Download (ext.)
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2007 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472743J. Hagemeyer, et al., “A Design Methodology for Communication Infrastructures on Partially Reconfigurable FPGAS”, Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL), IEEE Circuits and Systems Society and Technische Universiteit Delft, eds., Amsterdam, Netherlands: IEEE, 2007, pp.331-338.PUB | DOI
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2007 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472748J. Hagemeyer, et al., “INDRA – Integrated Design Flow for Reconfigurable Architectures”, Proceedings of the Conference on Design, Automation and Test in Europe (DATE '07) – University Booth, 2007.PUB | Download (ext.)
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2007 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2289033
M. Hussmann, et al., “Compiler-Driven Reconfiguration of Multiprocessors”, Proceedings of the Workshop on Application Specific Processors (WASP) 2007, 2007.PUB | PDF | Download (ext.)
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2007 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2289057T. Jungeblut, et al., “Real-Time Multiprocessor SoC for Mobile Ad Hoc Networks”, Proceedings of the Conference on Design, Automation and Test in Europe (DATE '07) – University Booth, 2007, 2007.PUB | Download (ext.)
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2007 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494165C. Paiz, B. Kettelhoit, and M. Porrmann, “A design framework for FPGA-based dynamically reconfigurable digital controllers”, Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS2007), Institute of Electrical and Electronics Engineers, ed., Piscataway, NJ: IEEE, 2007, pp.3709-3711.PUB | DOI
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2007 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494230T. Pfau, et al., “PDL-Tolerant Real-time Polarization-Multiplexed QPSK Transmission with Digital Coherent Polarization Diversity Receiver”, Proceedings of the 2007 IEEE/LEOS Summer Topical Meetings, IEEE Lasers and Electro-Optics Society, ed., Piscataway, NJ: IEEE, 2007, pp.17-18.PUB | DOI
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2007 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494285T. Pfau, et al., “Polarization-Multiplexed 2.8 Gbit/s Synchronous QPSK Transmission with Real-Time Digital Polarization Tracking”, Proceedings of ECOC, vol. 3, IEE, 2007, pp.263-264.PUB | DOI | Download (ext.)
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2007 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494514M. Porrmann, “Flexible Hardware Platforms for Dynamic Reconfiguration”, Invited Talk at the 2nd Int. Conf. on Industrial and Information Systems (ICIIS 2007), Reconfigurable Computing Workshop, 2007.PUB
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2007 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2285993V. Rana, et al., “Partial Dynamic Reconfiguration in a Multi-FPGA Clustered Architecture Based on Linux”, Proceedings of the 21st International Parallel and Distributed Processing Symposium (IPDPS 2007) - Reconfigurable Architecture Workshop (RAW), IEEE Computer Society., IEEE Computer Society. Technical Committee on Parallel Processing and Institute of Electrical and Electronics Engineers. Technical Committee on Parallel Processing, eds., Piscataway, NJ: IEEE, 2007.PUB | DOI
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2007 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494159C. Pohl, C. Paiz, and M. Porrmann, “Hardware-in-the-Loop Entwicklungsumgebung fuer informationsverarbeitende Komponenten mechatronischer Systeme”, 5. Paderborner Workshop Entwurf mechatronischer Systeme, 2007, pp.69-79.PUB
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2007 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494202R. Noe, et al., “Real-time Digital Carrier & Data Recovery for a Synchronous Optical Quadrature Phase Shift Keying Transmission System”, Proceedings of System Microwave Symposium. IEEE/MTT-S International, IEEE Microwave Theory and Techniques Society, ed., Piscataway, NJ: IEEE, 2007, pp.1503-1506.PUB | DOI
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2007 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494512M. Porrmann, “A Layer-Model Based Methodology for the Design of Dynamically Reconfigurable Systems. Invited Talk”, 2nd Int. Conf. on Industrial and Information Systems (ICIIS 2007), Reconfigurable Computing Workshop, 2007.PUB
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2007 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2289049J.-C. Niemann, et al., “A Multiprocessor Cache for Massively Parallel SoC Architectures”, ARCS'07: Architecture of Computing Systems, P. Lukowicz, ed., Lecture Notes in Computer Science, vol. 4415, Zurich, Switzerland: Springer Berlin Heidelberg, 2007, pp.83-97.PUB | DOI
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2006 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494328S. Hoffmann, et al., “Hardware-Efficient and Phase Noise Tolerant Digital Synchronous QPSK Receiver Concept”, Proceedings Optical Amplifiers and Their Applications/Coherent Optical Technologies and Applications, Optical Society of America, 2006.PUB | DOI | Download (ext.)
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2006 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494326H. Kalte and M. Porrmann, “REPLICA2Pro: Task Relocation by Bitstream Manipulation in VIRTEX-II/Pro FPGAs”, Proceedings of the 3rd Conference on Computing Frontiers, M. Alderighi, ed., New York: ACM, 2006, pp.403-412.PUB | DOI | Download (ext.)
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2006 | Sammelwerksbeitrag | Veröffentlicht | PUB-ID: 2285718M. Porrmann, U. Witkowski, and U. Rückert, “Implementation of Self-Organizing Feature Maps in Reconfigurable Hardware”, FPGA Implementations of Neural Networks, A. Omondi and J. Rajapakse, eds., Boston, MA: Springer, 2006, pp.247-269.PUB | DOI
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2006 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494321M. Porrmann and J.-C. Niemann, “Teaching Reconfigurable Computing Theory and Practice”, International Workshop on Reconfigurable Computing Education (on CD), 2006.PUB
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2006 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494340M. Koester, H. Kalte, and M. Porrmann, “Relocation and Defragmentation for Heterogeneous Reconfigurable Systems”, Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA '06), CSREA Press, 2006, pp.70-76.PUB
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2006 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494364B. Kettelhoit and M. Porrmann, “A Layer Model for Systematically Designing Dynamically Reconfigurable Systems”, Proceedings of the 16th International Conference on Field Programmable Logic and Applications, IEEE Circuits and Systems Society and Escuela Politécnica Superior (Madrid), eds., Piscataway, NJ: IEEE, 2006, pp.547-552.PUB | DOI
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2006 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2473942J. Hagemeyer, B. Kettelhoit, and M. Porrmann, “Dedicated Module Access in Dynamically Reconfigurable Systems”, Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS), Association for Computing Machinery, ed., ACM Digital Library, Washington, DC: IEEE, 2006, pp.1.PUB | DOI
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2006 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494374B. Griese, B. Kettelhoit, and M. Porrmann, “Evaluation of on-chip interfaces for dynamically reconfigurable coprocessors”, Proceedings of the 5th International Symposium on Parallel Computing in Electrical Engineering, IEEE Computer Society. Technical Committee on Parallel Processing and Institute of Electrical and Electronics Engineers. Poland Section, eds., Los Alamitos, Calif. : IEEE, 2006, pp.214-219.PUB | DOI
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2006 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494380C. Sauer, et al., “Application-driven Development of Concurrent Packet Processing Platforms”, Proceedings of the 5th International Symposium on Parallel Computing in Electrical Engineering, 2006, pp.55-61.PUB | Download (ext.)
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2006 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494368C. Paiz, C. Pohl, and M. Porrmann, “Reconfigurable Hardware in-the-Loop Simulations for Digital Control Design”, 3th International Conference on Informatics in Control, Automation and Robotics (ICINCO), 2006, pp.39-46.PUB
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2006 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2288961J.-C. Niemann, et al., “GigaNetIC – A Scalable Embedded On-Chip Multiprocessor Architecture for Network Applications”, ARCS'06 Architecture of Computing Systems, W. Grass, ed., Lecture notes in computer science, vol. 3894, Berlin, Heidelberg: Springer Berlin Heidelberg, 2006, pp.268-282.PUB | DOI
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2006 | Patent | Veröffentlicht | PUB-ID: 2494093J.-C. Niemann, et al., “Flexible Beschleunigungseinheit für die Verarbeitung von Datenpaketen”, 2006.PUB
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2006 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494346S. Hoffmann, et al., “Synchrone 1,6-Gbits-QPSK-Datenübertragung in Echtzeit mit DFB-Lasern”, Workshop der ITG Fachgruppe 5.3.1, Modellierung photonischer Komponenten und Systeme, 2006, pp.21-27.PUB
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2006 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2286278B. Jäger, M. Porrmann, and U. Rückert, “Bio-inspired massively parallel architectures for nanotechnologies”, Proceeding of the IEEE International Symposium on Circuits and Systems (ISCAS 2006)., IEEE Circuits and Systems Society, ed., Piscataway, NJ: IEEE, 2006, pp.1961-1964.PUB | DOI
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2006 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2288969
C. Sauer, et al., “A Lightweight NoC for the NOVA Packet Processing Plattform”, Design, Automation and Test in Europe DATE, Future Interconnect and Network-on-Chip (NoC) Workshop, Munich, Germany: 2006.PUB | PDF | Download (ext.)
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2005 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2288882
R. Eickhoff, et al., “Adaptable Switch boxes as on-chip routing nodes for networks-on-chip”, From Specification to Embedded Systems Application , A. Rettberg, M.C. Zanella, and F.J. Rammig, eds., IFIP On-Line Library in Computer Science, vol. 184, Boston, MA: Springer, 2005, pp.201-210.PUB | PDF | DOI | Download (ext.)
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2005 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494412B. Griese, S. Oberthür, and M. Porrmann, “Component case study of a self-optimizing RCOS/RTOS system. A reconfigurable network service”, From Specification to Embedded Systems Application, A. Rettberg, M.C. Zanella, and F.J. Rammig, eds., IFIP On-Line Library in Computer Science , vol. 184, Boston, MA: Springer, 2005, pp.267-277.PUB | DOI | Download (ext.)
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2005 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2288910C. Liß, et al., “Technologieplanung in der Mikroelektronik – von Moore's Law zur Nanotechnologie-Roadmap”, Symposium fuer Vorausschau und Technologieplanung, Berlin, Germany: 2005, pp.87-103.PUB
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2005 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494437M. Koester, H. Kalte, and M. Porrmann, “Task Placement for Heterogeneous Reconfigurable Architectures”, Proceedings of the IEEE 2005 Conference on Field-Programmable Technology (FPT '05), IEEE Circuits and Systems Society. Singapore Chapter, et al., eds., Piscataway, NJ: IEEE, 2005, pp.43-50.PUB | DOI
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2005 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494424H. Kalte and M. Porrmann, “Context Saving and Restoring for Multitasking in Reconfigurable Systems”, 15th International Conference on Field Programmable Logic and Applications, IEEE Circuits and Systems Society and Tampereen Teknillinen Yliopisto, eds., Piscataway, NJ: IEEE, 2005, pp.223-228.PUB | DOI
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2005 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494429M. Koester, H. Kalte, and M. Porrmann, “Run-Time Defragmentation for Partially Reconfigurable Systems”, Proceedings of the International Conference on Very Large Scale Integration (IFIP VLSI-SOC), 2005, pp.109-115.PUB
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2005 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2288900B. Kettelhoit, et al., “Rekonfigurierbare Hardware zur Regelung mechatronischer Systeme”, 3. Paderborner Workshop: Intelligente mechatronische Systeme, 2005, pp.195-205.PUB
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2005 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2286050M. Koester, M. Porrmann, and U. Rückert, “Placement-Oriented Modeling of Partially Reconfigurable Architectures”, Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005) - Reconfigurable Architectures Workshop (RAW), IEEE Computer Society, on CD., 2005.PUB | Download (ext.)
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2005 | Sammelwerksbeitrag | Veröffentlicht | PUB-ID: 2145286M. Grünewald, et al., “A framework for design space exploration of resource efficient network processing on multiprocessor SoCs”, Network Processor Design: Issues and Practices, P. Crowely, et al., eds., vol. 3, Morgan Kaufmann Publisher, 2005, pp.245-277.PUB | DOI
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2005 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2288853
J.-C. Niemann, et al., “An Evaluation of the Scalable GigaNetIC Architecture for Access Networks”, Advanced Networking and Communications Hardware Workshop (ANCHOR), held in conjunction with the 32nd Annual International Symposium on Computer Architecture (ISCA 2005), 2005.PUB | PDF
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2005 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2288944C. Paiz, et al., “Dynamically reconfigurable hardware for digital controllers in mechatronic systems”, IEEE International Conference on Mechatronics (ICM 2005), IEEE Industrial Electronics Society, ed., Piscataway, NJ: IEEE, 2005, pp.675-680.PUB | DOI
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2005 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2288829B. Kettelhoit, et al., “Dynamically Reconfigurable Hardware for Self-Optimizing Mechatronic Systems”, 5. GMM/ITG/GI-Workshop Multi-Nature Systems, 2005, pp.97-101.PUB
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2005 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2286119H. Kalte, et al., “REPLICA: A Bitstream Manipulation Filter for Module Relocation in Partial Reconfigurable Systems”, Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005) - Reconfigurable Architectures Workshop (RAW), IEEE Computer Society, on CD., IEEE, 2005.PUB | DOI
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2004 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494463G. Hagen, et al., “Developing an IP-DSLAM Benchmark for Network Processor Units”, ANCHOR 2004, Advanced Networking and Communications Hardware Workshop, held in conjunction with the 31st Annual International Symposium on Computer Architecture (ISCA 2004), 2004.PUB
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2004 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2285912E. Vonnahme, et al., “Dynamic Reconfiguration of Real-Time Network Interfaces”, Parallel Computing in Electrical Engineering, 2004. PARELEC 2004. International Conference on, IEEE Computer Society. Technical Committee on Parallel Processing and Technische Universität Dresden. Technical Committee on Parallel Processing, eds., Los Alamitos, Calif. : IEEE Comput. Soc, 2004, pp.376-379.PUB | DOI
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2004 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2288708H. Kalte, M. Porrmann, and U. Rückert, “Leistungsbewertung unterschiedlicher Einbettungsvarianten dynamisch rekonfigurierbarer Hardware”, ARCS 2004 – Organic and Pervasive Computing, 2004, pp.234-244.PUB
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2004 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2288760E. Vonnahme, et al., “Dynamische Rekonfiguration echtzeitfähiger Netzwerkschnittstellen”, VDE Kongress 2004 – ITG Fachtagung 'Ambient Intelligence', Berlin, Germany: VDE Verlag, 2004, pp.99-104.PUB
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2004 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2286101M. Grunewald, et al., “A mapping strategy for resource-efficient network processing on multiprocessor SoCs”, Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings, European Design Automation Association, ed., vol. 2, Los Alamitos, Calif. : IEEE Comput. Soc, 2004, pp.758-763.PUB | DOI
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2004 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2286233H. Kalte, et al., “Study on column wise design compaction for reconfigurable systems”, Field-Programmable Technology, 2004. Proceedings. 2004 IEEE International Conference on, IEEE Electron Devices Society and School of Information Technology and Electrical Engineering, eds., Piscataway, NJ: IEEE, 2004, pp.413-416.PUB | DOI
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2004 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2288776J.-C. Niemann, M. Porrmann, and U. Rückert, “Parallele Architekturen für Netzwerkprozessoren”, Ambient Intelligence, VDE Kongress, vol. 1, VDE Verlag, 2004, pp.105-110.PUB | Download (ext.)
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2004 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2288730H. Kalte, et al., “A Comparative Study on System Approaches for Partially Reconfigurable Architectures”, Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA '04), T. Plaks, ed., Las Vegas, Nevada, USA: CSREA Press, 2004, pp.70-76.PUB
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2004 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2288742B. Griese, et al., “Hardware Support for Dynamic Reconfiguration in Reconfigurable SoC Architectures”, Proceedings of the 14th International Conference on Field Programmable Logic and its Applications (FPL2004), J. Becker, ed., Lecture notes in computer science, vol. 3203, Antwerp, Belgium: Springer Berlin Heidelberg, 2004, pp.842-846.PUB | DOI
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2004 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2286146M. Grunewald, et al., “Network application driven instruction set extensions for embedded processing clusters”, Parallel Computing in Electrical Engineering, 2004. PARELEC 2004. International Conference on, IEEE Computer Society. Technical Committee on Parallel Processing and Technische Universität Dresden. Technical Committee on Parallel Processing, eds., Los Alamitos, Calif. : IEEE Comput. Soc, 2004, pp.209-214.PUB | DOI
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2004 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2288700M. Grünewald, et al., “A framework for design space exploration of resource efficient network processing on multiprocessor SoCs”, Proceedings of the 3rd Workshop on Network Processors & Applications, Madrid, Spain: 2004, pp.87-101.PUB
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2004 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2285942M. Franzmeier, et al., “Hardware Accelerated Data Analysis”, Parallel Computing in Electrical Engineering, 2004. PARELEC 2004. International Conference on, IEEE Computer Society. Technical Committee on Parallel Processing and Technische Universität Dresden. Technical Committee on Parallel Processing, eds., Los Alamitos, Calif. : IEEE Comput. Soc, 2004, pp.309-314.PUB | DOI
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2004 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2286138C. Pohl, et al., “gNBX - reconfigurable hardware acceleration of self-organizing maps”, Field-Programmable Technology, 2004. Proceedings. 2004 IEEE International Conference on, IEEE Electron Devices Society and School of Information Technology and Electrical Engineering, eds., Piscataway, NJ: IEEE, 2004, pp.97-104.PUB | DOI
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2003 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2145324M. Porrmann, U. Witkowski, and U. Rückert, “A Massively Parallel Architecture for Self-Organizing Feature Maps”, IEEE Transactions on Neural Networks, Special Issue on Hardware Implementations, vol. 14, 2003, pp. 1110-1121.PUB | DOI | WoS | PubMed | Europe PMC
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2002 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2288575H. Kalte, M. Porrmann, and U. Rückert, “A Prototyping Platform for Dynamically Reconfigurable System on Chip Designs”, Proceedings of the IEEE Workshop Heterogeneous reconfigurable Systems on Chip (SoC), Hamburg, Germany: 2002.PUB
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2002 | Monographie | Veröffentlicht | PUB-ID: 2493620M. Porrmann, Leistungsbewertung eingebetteter Neurocomputersysteme. Dissertation., vol. 104, Paderborn: HNI-Verlagsschriftenreihe, Heinz Nixdorf Institut, Schaltungstechnik, 2002.PUB
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2002 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2288589M. Porrmann, et al., “Dynamically Reconfigurable Hardware – A New Perspective for Neural Network Implementations”, Proceedings of the International Conference on Field Programmable Logic and Applications (FPL2002), M. Glesner, ed., Lecture notes in computer science, vol. 2438, Montpellier, France: Springer Berlin Heidelberg, 2002, pp.1048-1057.PUB | DOI
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2002 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2285896M. Porrmann, et al., “Implementation of artificial neural networks on a reconfigurable hardware accelerator”, Parallel, Distributed and Network-based Processing, 2002. Proceedings. 10th Euromicro Workshop on, IEEE Comput. Soc, 2002, pp.243-250.PUB | DOI
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2001 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2288549M. Porrmann, S. Rüping, and U. Rückert, “The Impact of Communication on Hardware Accelerators for Neural Networks”, Proceedings of The 5th World Multi-Conference on Systemics, Cybernetics and Informatics (SCI), vol. 3, Orlando, Florida, USA: 2001, pp.248-253.PUB
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2001 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2288526M. Porrmann, et al., “XipChip – A Multiprocessor CPU for Multifunction Peripherals”, Proceedings of The 5th World Multi-Conference on Systemics, Cybernetics and Informatics (SCI), vol. 15, Orlando, Florida, USA: 2001, pp.512-517.PUB
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2001 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2288539M. Porrmann, et al., “A Dynamically Reconfigurable Hardware Accelerator for Self-Organizing Feature Maps”, Proceedings of The 5th World Multi-Conference on Systemics, Cybernetics and Informatics, SCI 2001, vol. 3, Orlando, Florida, USA: 2001, pp.242-247.PUB
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2000 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2286566H. Kalte, M. Porrmann, and U. Rückert, “Rapid Prototyping System für dynamisch rekonfigurierbare Hardwarestrukturen”, Workshop: Architekturentwurf und Entwicklung eingebetteter Systeme (AES2000), Karlsruhe, Germany: 2000, pp.149-157.PUB
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2000 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2286572H. Kalte, M. Porrmann, and U. Rückert, “Using a Dynamically Reconfigurable System to Accelerate Octree Based 3D Graphics”, Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA´2000), vol. 5, Monte Carlo Resort, Las Vegas, Nevada, USA: 2000, pp.2819-2824.PUB
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1999 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2286315M. Porrmann, S. Ruping, and U. Rückert, “SOM hardware with acceleration module for graphical representation of the learning process”, Microelectronics for Neural, Fuzzy and Bio-Inspired Systems, 1999. MicroNeuro '99. Proceedings of the Seventh International Conference on, IEEE Comput. Soc, 1999, pp.380-386.PUB | DOI
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1998 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2286468M. Porrmann, et al., “A Hybrid Knowledge Processing System”, Proceedings of the Conference Neural Networks and their Applications (NEURAP), Marseille, France: 1998, pp.177-184.PUB
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1998 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2285592S. Rüping, M. Porrmann, and U. Rückert, “SOM Accelerator System”, Neurocomputing, vol. 21, 1998, pp. 31-50.PUB | Download (ext.)
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1997 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2286384
S. Rüping, M. Porrmann, and U. Rückert, “A High Performance SOFM Hardware-System”, Proceedings of the International Work-Conference on Artificial and Natural Neural Networks (IWANN´97), Lanzarote, Spain: 1997, pp.772-781.PUB | PDF | Download (ext.)
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1997 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2286402
S. Rüping, M. Porrmann, and U. Rückert, “SOM Hardware-Accelerator”, Workshop on Self-Organizing Maps (WSOM), Espoo, Finnland: 1997, pp.136-141.PUB | PDF | Download (ext.)
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1996 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2285575G. Palm, et al., “Neuronale Assoziativspeicher”, Neuroinformatik Statusseminar, 1996, pp.419-432.PUB