66 Publikationen
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2023 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2985997
M. Flasskamp, C. Klarhorst, and J. Hagemeyer, “Trustworthy System-on-Chip by monitoring system behavior at runtime”, Proceedings of the 1st Safety and Security in Heterogeneous Open System-on-Chip Platforms Workshop (SSH-SoC 2023), F. Restuccia, et al., eds., 2023.PUB | PDF | Download (ext.) -
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2023 | Sammelwerksbeitrag | Veröffentlicht | PUB-ID: 2983268M. Kortekamp, et al., “A Scalable Binary Neural Associative Memory on FPGA”, Advances in Computational Intelligence. 17th International Work-Conference on Artificial Neural Networks, IWANN 2023, Ponta Delgada, Portugal, June 19–21, 2023, Proceedings, Part I, I. Rojas, G. Joya, and A. Catala, eds., Lecture Notes in Computer Science, Cham: Springer Nature Switzerland, 2023, pp.381-393.PUB | DOI
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2022 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2964196M. Kaiser, et al., “VEDLIoT: Very Efficient Deep Learning in IoT”, DATE '22: Proceedings of the 2022 Conference & Exhibition on Design, Automation & Test in Europe, Institut of Electrical and Electronics Engineers (IEEE), ed., Leuven: European Design and Automation Association, 2022, pp.963-968.PUB | DOI
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2020 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2941646
S. Pilz, et al., “Accelerating Binary String Comparisons with a Scalable, Streaming-Based System Architecture Based on FPGAs”, Algorithms, vol. 13, 2020, : 47.PUB | PDF | DOI | Download (ext.) | WoS
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2019 | Sammelwerksbeitrag | Veröffentlicht | PUB-ID: 2920469A. Oleksiak, et al., “M2DC – A Novel Heterogeneous Hyperscale Microserver Platform”, Hardware Accelerators in Data Centers, C. Kachris, B. Falsafi, and D. Soudris, eds., 1st ed., Cham, Switzerland: Springer International Publishing AG, 2019, pp.109-128.PUB | DOI
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2018 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2982045A. Cristal, et al., “LEGaTO. First steps towards energy-efficient toolset for heterogeneous computing”, SAMOS '18. Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, New York, NY: ACM, 2018, pp.210-217.PUB | DOI
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2018 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2979448A. Cristal, et al., “LEGaTO. First steps towards energy-efficient toolset for heterogeneous computing”, Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, T. Mudge, ed., New York, NY, USA: ACM, 2018, pp.210-217.PUB | DOI
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2018 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2955564A. Cristal, et al., “LEGaTO Project: Towards Energy-Efficient, Secure, Fault-tolerant Toolset for Heterogeneous Computing.”, Proceedings of the 15th ACM International Conference on Computing Frontiers, D. Kaeli, ed., New York, NY: ACM, 2018, pp.276-278.PUB | DOI | Download (ext.)
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2018 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2940681D. Klimeck, et al., “Resource-efficient Reconfigurable Computer-on-Module for Embedded Vision Applications”, 2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP), Piscataway, NJ: IEEE, 2018.PUB | DOI
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2018 | Kurzbeitrag Konferenz / Poster | Veröffentlicht | PUB-ID: 2918788
M. Kaiser, et al., “Accelerating Hamming Distance Comparisons for Locality Sensitive Hashing (LSH) using FPGAs”, 12th CeBiTec Symposium - Big Data in Medicine and Biotechnology - Abstract Book, vol. 12, Bielefeld: 2018, pp.48-49.PUB | PDF
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2017 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2937407G. Agosta, et al., “The M2DC Approach towards Resource-efficient Computing”, OPPORTUNITIES AND CHALLENGES for European Projects. Volume 1: EPS Portugal 2017/2018, A. Bagnato, et al., eds., Setúbal, Portugal: SCITEPRESS, 2017, pp.150-176.PUB | DOI
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2017 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2909430A. Irwansyah, et al., “FPGA-based Multi-Robot Tracking”, Journal of Parallel and Distributed Computing, vol. 107, 2017, pp. 146-161.PUB | DOI | Download (ext.) | WoS
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2017 | Kurzbeitrag Konferenz / Poster | Veröffentlicht | PUB-ID: 2918683
M. Kaiser, et al., “A Reconfigurable Heterogeneous Microserver Architecture for Energy-efficient Computing”, Third International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC'17), Denver, CO: 2017.PUB | PDF | Download (ext.)
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2017 | Konferenzbeitrag | PUB-ID: 2909584A. Oleksiak, et al., “M2DC: Modular Microserver Datacentre with Heterogeneous Hardware”, Presented at the Energy-efficient Servers for Cloud and Edge Computing 2017 Workshop (ENeSCE 2017) - co-located with HiPEAC 2017, Stockholm, Sweden, 2017.PUB
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2017 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2915029J. Tlatlik, et al., “Entwurf eines FPGA-basierten Verbindungsknotens als Prototypenumgebung für energieeffiziente und sichere Gebäudeautomationssysteme”, Tag des Systems Engineering: Paderborn, 8. -10. November 2017, S.-O. Schulze, et al., eds., München: Carl Hanser Verlag GmbH Co KG, 2017, pp.55-- 64.PUB
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2017 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2909044J. Lachmair, et al., “From CPU to FPGA – Acceleration of Self-Organizing Maps for Data Mining”, International Joint Conference on Neural Networks (IJCNN 2017), 2017, pp.4299-4308.PUB
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2016 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2903257
M. Kierzynka, et al., “Energy Efficiency of Sequence Alignment Tools - Software and Hardware Perspectives”, Future Generation Computer Systems, vol. 67, 2016, pp. 455-465.PUB | PDF | DOI | Download (ext.) | WoS
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2016 | Kurzbeitrag Konferenz / Poster | PUB-ID: 2909602R. Griessl, et al., “FiPS and M2DC: Novel Architectures for Reconfigurable Hyperscale Servers”, Presented at the Workshop "Reconfigurable Computing — From Embedded Systems to Reconfigurable Hyperscale Servers" co-located with the International Conference on Field-Programmable Logic and Applications (FPL 2016), Lausanne, Switzerland, 2016.PUB | Download (ext.)
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2015 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2901107O.W. Ibraheem, et al., “A resource-efficient multi-camera GigE vision IP core for embedded vision processing platforms”, 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), M. Hübner, M. Gokhale, and R. Cumplido, eds., Piscataway, NJ: IEEE, 2015, pp.1-6.PUB | DOI
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2015 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2901108A. Irwansyah, et al., “FPGA-based circular hough transform with graph clustering for vision-based multi-robot tracking”, 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), M. Hübner, M. Gokhale, and R. Cumplido, eds., Piscataway, NJ: IEEE, 2015, pp.1-8.PUB | DOI
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2015 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2902039
R. Griessl, et al., “FPGA-accelerated Heterogeneous Hyperscale Server Architecture for Next-Generation Compute Clusters”, Presented at the First International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC‘15), held in conjunction with Supercomputing 2015, Austin Texas, USA, 2015.PUB | PDF
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2014 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2681323D. Sabena, et al., “Reconfigurable High Performance Architectures: How much are they ready for safety-critical applications”, Proceedings of 19th IEEE European Test Symposium (ETS), IEEE, 2014, pp.175-182.PUB | DOI | Download (ext.)
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2014 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2698999D. Sorrenti, et al., “Exploiting Dynamic Partial Reconfiguration for On-Line On-Demand Testing of Permanent Faults in Reconfigurable Systems”, Presented at the 17th IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Amsterdam, The Netherlands, 2014.PUB | DOI | Download (ext.)
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2014 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2699005D. Cozzi, et al., “AXI-based SpaceFibre IP CORE Implementation”, Presented at the 6th International SpaceWire Conference, Athens, Greece, 2014.PUB | DOI | Download (ext.)
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2014 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2698930R. Griessl, et al., “A Scalable Server Architecture for Next-Generation Heterogeneous Compute Clusters”, Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, EUC 2014, IEEE, 2014, pp.146-153.PUB | DOI | Download (ext.)
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2014 | Konferenzbeitrag | PUB-ID: 2681362L. Cassano, et al., “An Inter-Processor Communication Interface for Data-Flow Centric Heterogeneous Embedded Multiprocessor Systems”, Presented at the DTIS 2014, 9th International conference on Design & Technology of Integrated Systems in Nanoscale Era, Santorini , Greece, 2014.PUB | DOI | Download (ext.)
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2013 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2576115
S. Korf, et al., “Dynamisch rekonfigurierbare Hardware als Basistechnologie für intelligente technische Systeme”, Proceedings Wissenschaftsforum 2013 Intelligente Technische Systeme, J. Gausemeier, et al., eds., HNI-Verlagsschriftenreihe, vol. 310, Paderborn: Heinz-Nixdorf-Inst., Univ. Paderborn, 2013, pp.79-90.PUB | PDF
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2013 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2681289M. Desogus, et al., “Hardening Dynamically Reconfigurable Processing Modules Architectures: A Neutron Test Experience”, RADECS proceedings, vol. 2, IEEE / Institute of Electrical and Electronics Engineers, 2013, pp.13-16.PUB
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2013 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2681304L. Sterpone, et al., “Dynamic neutron testing of Dynamically Reconfigurable Processing Modules architecture”, Adaptive Hardware and Systems (AHS), 2013 NASA/ESA Conference on, IEEE, 2013, pp.184-188.PUB | DOI | Download (ext.)
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2012 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2517354J. Hagemeyer, et al., “A Scalable Platform for Run-time Reconfigurable Satellite Payload Processing”, 2012 NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2012), Piscataway, NJ: IEEE, 2012, pp.9-16.PUB | DOI | Download (ext.)
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2011 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2286173S. Korf, et al., “Automatic HDL-Based Generation of Homogeneous Hard Macros for FPGAs”, IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2011 : 1 - 3 May 2011, Salt Lake City, Utah, USA ; proceedings , P. Chow, ed., Piscataway, NJ: IEEE, 2011, pp.125-132.PUB | DOI | Download (ext.)
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2011 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2493823M. Grawinkel, et al., “Evaluation of Applied Intra-Disk Redundancy Schemes to Improve Single Disk Reliability.”, MASCOTS2011 The 19th Annual Meeting of the IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems., Association for Computing Machinery, Institute of Electrical and Electronics Engineers, and Nanyang Technological University, eds., Piscataway, NJ: IEEE, 2011, pp.297-306.PUB | DOI | Download (ext.)
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2011 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2493819L. Sterpone, et al., “Analysis of SEU Effects in Partially Reconfigurable SoPCs.”, Proceedings of NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2011), European Space Agency, et al., eds., Piscataway, NJ: IEEE, 2011, pp.129-136.PUB | DOI
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2011 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494507J. Romoth, et al., “Fast Design-space Exploration with FPGA Cluster”, DATE 2011 Workshop on Design Methods and Tools for FPGA-Based Acceleration of Scientific Computing, 2011.PUB | Download (ext.)
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2011 | Kurzbeitrag Konferenz / Poster | Veröffentlicht | PUB-ID: 2494497M. Köster, et al., “Design Flow for a Fault-Tolerant Reconfigurable Multi-FPGA Architecture for Space Applications”, DATE 2011 Workshop on Design Methods and Tools for FPGA-Based Acceleration of Scientific Computing, 2011.PUB
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2010 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2493826F. Dittmann, et al., “Implementation of a Dynamically Reconfigurable Processing Module for SpaceWire Networks.”, Proceedings of the International SpaceWire Conference 2010, 2010, pp.193-196.PUB | Download (ext.)
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2010 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472693
M. Porrmann, et al., “RAPTOR – A Scalable Platform for Rapid Prototyping and FPGA-based Cluster Computing”, Parallel Computing: From Multicores and GPU's to Petascale, Advances in Parallel Computing, vol. 19, IOS press, 2010, pp.592-599.PUB | PDF
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2010 | Patent | Veröffentlicht | PUB-ID: 2494087W. Christmann, et al., “Mehrprozessor-Computersystem”, 2010.PUB
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2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472673M. Koester, et al., “Design Optimizations to Improve Placeability of Partial Reconfiguration Modules”, Proceedings of the International Conference on Design, Automation and Test in Europe (DATE 2009), European Design Automation Association, ed., Piscataway, NJ: ACM Press, 2009.PUB | DOI | Download (ext.)
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2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472678M. Porrmann, et al., “Rapid Prototyping of Next-Generation Multiprocessor SoCs”, Proceedings of Semiconductor Conference Dresden, SCD 2009, Dresden, Germany: 2009.PUB
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2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472686P.R. Grassi, et al., “SiLLis: A Simplified Language for Monitoring and Debugging of Reconfigurable Systems”, Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA '09), Las Vegas, USA: 2009, pp.174-180.PUB
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2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2144891C. Paiz, et al., “FPGA-in-the-Loop-Simulations for Dynamically Reconfigurable Applications”, Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT'09), IEEE Circuits and Systems Society, IEEE Electron Devices Society, and Institute of Electrical and Electronics Engineers, eds., The University of New South Wales, Sydney, Australia, 9-11, Sydney, Australia: IEEE, 2009, pp.372-375.PUB | DOI
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2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2144880C. Pohl, et al., “Using a Reconfigurable Compute Cluster for the Acceleration of Neural Networks”, Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT '09), IEEE Circuits and Systems Society, IEEE Electron Devices Society, and Institute of Electrical and Electronics Engineers, eds., Sydney, Australia: IEEE, 2009, pp.368-371.PUB | DOI
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2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2144843
C. Paiz, et al., “FPGA-Based Realization of Self-Optimizing Drive-Controllers”, the 35th Annual Conference of the IEEE Industrial Electronics Society (IECON 2009), IEEE Industrial Electronics Society, et al., eds., Piscataway, NJ: IEEE, 2009, pp.2868-2873.PUB | PDF | DOI | Download (ext.)
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2008 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472725J. Hagemeyer, M. Koester, and M. Porrmann, “Hardware Virtualization Exploiting Dynamically Reconfigurable Architectures”, 1. GI/ITG KuVS Fachgespräch Virtualisierung, Heinz Nixdorf Institut, Universität Paderborn, 2008.PUB
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2007 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472738J. Hagemeyer, et al., “Design of Homogeneous Communication Infrastructures for Partially Reconfigurable FPGAs”, Proc. of the Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA '07), Las Vegas, USA: 2007.PUB | Download (ext.)
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2007 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472743J. Hagemeyer, et al., “A Design Methodology for Communication Infrastructures on Partially Reconfigurable FPGAS”, Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL), IEEE Circuits and Systems Society and Technische Universiteit Delft, eds., Amsterdam, Netherlands: IEEE, 2007, pp.331-338.PUB | DOI
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2007 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472748J. Hagemeyer, et al., “INDRA – Integrated Design Flow for Reconfigurable Architectures”, Proceedings of the Conference on Design, Automation and Test in Europe (DATE '07) – University Booth, 2007.PUB | Download (ext.)
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2006 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2473942J. Hagemeyer, B. Kettelhoit, and M. Porrmann, “Dedicated Module Access in Dynamically Reconfigurable Systems”, Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS), Association for Computing Machinery, ed., ACM Digital Library, Washington, DC: IEEE, 2006, pp.1.PUB | DOI